Test compression and logic BIST at your fingertips

Shianling Wu; Laung-Terng Wang; Jin Woo Cho; Zhigang Jiang; Boryau Sheu

doi:10.1109/TEST.2005.1584111

IEEE International Conference on Test, 2005.

Test compression and logic BIST at your fingertips

Year: 2005, Pages: 2 pp.-1285

DOI Bookmark: 10.1109/TEST.2005.1584111

Authors

Shianling Wu
Laung-Terng Wang
Jin Woo Cho
Zhigang Jiang
Boryau Sheu

Abstract

This paper describes two design-for-test (DFT) methods that provide flexibility in order to achieve desired test cost reduction goal using embedded scan compression and logic built-in self-test (BIST). In some applications, one method can be used in conjunction with the other.

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Test compression and logic BIST at your fingertips

Authors

Abstract

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