Abstract
Yield learning is more important to ASIC vendors than ever. The high cost of developing a 90 nm ASIC will result in a smaller number of high volume devices. Achieving yield goals during production ramp can be the difference between product success and failure. Yield and Product engineers are faced with all of the traditional fabrication issues, like particle related defects and device model matching, which have always made yield learning a challenge. Several new trends are taking hold with sub-130 nm processing that will make yield learning even more of a challenge in the future.