A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs

Vivek Chickermane; Patrick Gallagher; James Sage; Paul Yuan; Krishna Chakravadhanula

doi:10.1109/TEST.2008.4700572

2008 IEEE International Test Conference

A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs

Year: 2008

DOI Bookmark: 10.1109/TEST.2008.4700572

Authors

Vivek Chickermane, Front-End Design Group, Cadence Design Systems, USA. vivekc@cadence.com
Patrick Gallagher, Front-End Design Group, Cadence Design Systems, USA. patrickg@cadence.com
James Sage, Front-End Design Group, Cadence Design Systems, USA. sagejm@cadence.com
Paul Yuan, Front-End Design Group, Cadence Design Systems, USA. paulyuan@cadence.com
Krishna Chakravadhanula, Front-End Design Group, Cadence Design Systems, USA. ckrishna@cadence.com

Abstract

This paper describes the challenges of testing low-power designs that use the commonly used multi-supply multi-voltage (MSMV) and power shut-off (PSO) design methodology. We describe a novel solution to address the manufacturing test of an MSMV/PSO design by using power-mode specifications to map multiple power modes to their target test modes and enhancing the DFT and ATPG methodology to enable a comprehensive test methodology. We provide experimental results and future directions for power-aware test.

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A Power-Aware Test Methodology for Multi-Supply Multi-Voltage Designs

Authors

Abstract

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