Design-for-secure-test for crypto cores

Related Articles

• Dual Edge Triggered Flip-Flops for Noise Aware Design
  2011 16th IEEE European Test Symposium (ETS)
• A robust pulsed flip-flop and its use in enhanced scan design
  2009 IEEE International Conference on Computer Design
• A fault oriented partial scan design approach
  1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers
• Cost and power efficient timing error tolerance in flip-flop based microprocessor cores
  2012 17th IEEE European Test Symposium (ETS)
• Enabling LOS delay test with slow scan enable
  2016 IEEE East-West Design & Test Symposium (EWDTS)
• A controllable setup and propagation delay flip-flop design
  2015 16th Latin-American Test Symposium (LATS)
• An economical scan design for sequential logic test generation
  1989 The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers
• Robust secure scan design against scan-based differential cryptanalysis
  IEEE Transactions on Very Large Scale Integration (VLSI) Systems
• Design for Cost Effective Scan Testing by Reconfiguring Scan Flip-Flops
  14th Asian Test Symposium (ATS'05)
• Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits
  2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)