Abstract
Parasitic components of a MOSFET are mainly responsible for the intrinsic delay of logic gates, and they can be modelled with fairly high accuracy for gate delay estimation. The extraction of transistor parasitic from physical structure (mask layout) is also fairly straight forward. The first component of capacitive parasitic, we will examine is the MOSFET capacitances. The classical approach for determining the switching speed of the logic gates is based on the assumption that the loads are mainly capacitive and lumped. Relatively simple delay models exist for logic gates with purely capacitive load at the output node; hence the dynamic behaviour of the circuit can be estimated easily once the load is determined.