Abstract
Scan shift causes a lot of switching activity in the combinational logic that in turn can lead to high IR-drop. Excessive IR-drop may corrupt test vectors or responses during shifting, leading to test-induced yield-loss. Power-aware X-filling is a widely used method to reduce the overall switching activity during shifting without modifying the scan infrastructure. While such untargeted approaches help reduce the average IR-drop during shifting, some hot-spots of worst-case IR-drop still remain. Through an innovative in-depth IR-drop analysis of high-risk shift cycles, we discovered that these hot-spots are caused by a few High-Impact scan-cell Transitions (HITs). In this paper, we propose to reduce the peak IR-drop during scan shift by using a novel X-filling strategy that (1) identifies HITs through GPU-accelerated IR-drop estimation, and (2) adjusts the X-filling of test vectors to mitigate the remaining worst-case IR-drop hotspots. The results on ITC’99 benchmark circuits demonstrate a 26% peak IR-drop reduction on average without impact on fault coverage or test vector count.