Abstract
Summary form only given. We discuss different integration approaches, their challenges, and problems specific to the integration of ferroelectric materials into Si-CMOS. The focus is on our ongoing integration efforts using a 1 K test vehicle with 2T/2C memory architectures in single level poly and single level metal with a 0.8 /spl mu/m front-end and a 1.2 /spl mu/m back-end. The ferroelectric capacitor module comprises Pt electrodes and a layered perovskite SrBi/sub 2/Ta/sub 2/O/sub 9/ (SBT) dielectric. The capacitor module is integrated between the CMOS front-end and the metal back-end. This approach dictates processing temperatures below 900/spl deg/C during the ferroelectric module processing and below 450/spl deg/C after the metal deposition. Oxide ceramics like SET or PZT are easily damaged in plasma processes. Examples of such process damage and recovery by oxygen anneals are discussed. Progress in patterning capacitor materials is described. Finally, the post-metal anneal dilemma of not being able to perform hydrogen (i.e. forming gas) anneals for transistor recovery is discussed. Ferroelectric capacitor properties and transistor characteristics after integration are shown.