Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator

Mario Porrmann; Ulf Witkowski; Heiko Kalte; Ulrich Rückert

doi:10.1109/EMPDP.2002.994279

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10th Euromicro Workshop on Parallel, Distributed and Network-based Processing (EUROMICRO-PDP 2002)

Implementation of Artificial Neural Networks on a Reconfigurable Hardware Accelerator

Year: 2002, Pages: 0243

DOI Bookmark: 10.1109/EMPDP.2002.994279

Authors

Mario Porrmann, University of Paderborn
Ulf Witkowski, University of Paderborn
Heiko Kalte, University of Paderborn
Ulrich Rückert, University of Paderborn

Abstract

The hardware implementation of three different artificial neural networks is presented. The basis for the implementation is the reconfigurable hardware accelerator RAPTOR2000, which is based on FPGAs. The investigated neural network architectures are neural associative memories, self-organizing feature maps and basis function networks. Some of the key implementational issues are considered. Especially resource-efficiency and performance of the presented realizations are discussed.

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