Scan-Path with Directly Duplicated and Inverted Duplicated Registers

M. Goessel; E. Sogomonyan; A. Singh

doi:10.1109/VTS.2002.1011110

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Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

Scan-Path with Directly Duplicated and Inverted Duplicated Registers

Year: 2002, Pages: 0047

DOI Bookmark: 10.1109/VTS.2002.1011110

Authors

M. Goessel, University of Potsdam
E. Sogomonyan, University of Potsdam
A. Singh, Auburn University

Abstract

In this paper a systematic scan-path design with duplicated and inverted duplicated memory elements is proposed. Contrary to a known solution [1] no additional control lines for additional multiplexors are needed. Full controllability and observability of the proposed scan-path is demonstrated.

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