Towards supply-grid-based derating of timing margins

Lars Svensson; Johnny Pihl; Daniel A. Andersson; Bjorn Nilsson; Per Larsson-Edefors

doi:10.1109/SPI.2009.5089868

2009 IEEE Workshop on Signal Propagation on Interconnects (SPI)

Towards supply-grid-based derating of timing margins

Year: 2009

DOI Bookmark: 10.1109/SPI.2009.5089868

Authors

Lars Svensson, Dept of Computer Science and Engineering, Chalmers University of Technology, SE-412 96 Gothenburg, Sweden
Johnny Pihl, Atmel Norway AS, Vestre Rosten 79, 7075 Tiller, Norway
Daniel A. Andersson, Atmel Norway AS, Vestre Rosten 79, 7075 Tiller, Norway
Bjorn Nilsson, Dept of Computer Science and Engineering, Chalmers University of Technology, SE-412 96 Gothenburg, Sweden
Per Larsson-Edefors, Dept of Computer Science and Engineering, Chalmers University of Technology, SE-412 96 Gothenburg, Sweden

Abstract

We investigate the influence of a realistic supply voltage network on the timing margins for a commercially-available 32-bit processor chip. Detailed models of the supply network and switching activity produce a spatial map of the supply voltage waveforms. We relate these waveforms to the expected excess logic delays, and estimate the required derating of the critical setup paths.

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Towards supply-grid-based derating of timing margins

Authors

Abstract

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