Multiple fault diagnosis in printed circuit boards

S.J. Barnfield; W.R. Moore

doi:10.1109/TEST.1993.470637

Proceedings of IEEE International Test Conference - (ITC)

Multiple fault diagnosis in printed circuit boards

Year: 1993, Pages: 662,663,664,665,666,667,668,669,670,671

DOI Bookmark: 10.1109/TEST.1993.470637

Authors

S.J. Barnfield, Dept. of Eng. Sci., Oxford Univ., UK
W.R. Moore

Abstract

This paper addresses the problems of diagnosing multiple faults occuring in the non-boundary-scan parts of a printed circuit board. The paper details a diagnostic algorithm based upon combining the fault signatures of single faults in order to produce a pattern which best matches the signature of a multiple fault. In addition, a graphical routine is presented which allows the tester to analyze a given set of test vectors. This analysis provides an implicit fault-simulation process for stuck-at and bridging faults. Furthermore, the process informs the tester of any faults which mask other previously detectable faults within the given test set.<>

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Multiple fault diagnosis in printed circuit boards

Authors

Abstract

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