Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation

Anis Uzzaman; Bibo Li; Tom Snethen; Brion Keller; Gary Grise

doi:10.1109/TEST.2007.4437610

Previous
Next
Table of Contents
Similar Articles

International Test Conference 2007

Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation

Year: 2007

DOI Bookmark: 10.1109/TEST.2007.4437610

Authors

Anis Uzzaman, Cadence Design Systems, Inc., Endicott, New York 13760, USA
Bibo Li, Cadence Design Systems, Inc., Endicott, New York 13760, USA
Tom Snethen, Cadence Design Systems, Inc., Endicott, New York 13760, USA
Brion Keller, Cadence Design Systems, Inc., Endicott, New York 13760, USA
Gary Grise, International Business Machines, Inc., Burlington, Vermont, USA

Automated handling of programmable on-product clock generation (OPCG) circuitry for delay test vector generation

Authors

Abstract