Abstract
This paper describes the parallelization of a diagnostic fault simulator for stuck-at faults in sequential circuits. The parallelization is performed by partitioning the diagnostic equivalence classes obtained by simulating the first few test vectors of the test set. The partitions are then simulated in parallel, independent of each other for the remaining vectors. Thus there is no communication overhead. Results on performance speedup and diagnostic resolution loss are provided for the ISCAS 89 benchmark circuits.