Novel Architecture of EBC for JPEG2000

Anand Gautam; A. Geeta Madhuri; Priya Khandelwal; K. Pratyush Aditya; Meghana Desai; Padma N. Krishna; Malvika Dutt; Reeti Bhatia

doi:10.1109/VLSID.2006.121

VLSI Design, International Conference on

Novel Architecture of EBC for JPEG2000

Year: 2006, Pages: 530-533

DOI Bookmark: 10.1109/VLSID.2006.121

Authors

Anand Gautam, Dhirubhai Ambani Institute of Information and Communication Technology
A. Geeta Madhuri, Dhirubhai Ambani Institute of Information and Communication Technology
Priya Khandelwal, Dhirubhai Ambani Institute of Information and Communication Technology
K. Pratyush Aditya, Dhirubhai Ambani Institute of Information and Communication Technology
Meghana Desai, Dhirubhai Ambani Institute of Information and Communication Technology
Padma N. Krishna, Dhirubhai Ambani Institute of Information and Communication Technology
Malvika Dutt, Dhirubhai Ambani Institute of Information and Communication Technology
Reeti Bhatia, Dhirubhai Ambani Institute of Information and Communication Technology

Abstract

The paper presents a novel architecture of EBC (Embedded Block Coding) for JPEG2000. It presents three speed-up methods: bit-plane parallelization, three stage pipelined architecture of Context Formation block and three stage pipelined architecture of MQ encoder block. The proposed design would consequently enhance the throughput and reduce latency, enabling high speed compression. The synthesis and implementation of the design was done on 0.13? technology using Cadence RTL Compiler.

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Novel Architecture of EBC for JPEG2000

Authors

Abstract

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