An Efficient Method for Clock Skew Scheduling to Reduce Peak Current

Concurrent switching of flip-flops and logic gates produces a current surge in synchronous circuits resulting in power supply noise and integrity issues. It is well known that peak current caused by simultaneous switching can be reduced by clock skew scheduling. It has been shown that this problem may be formulated as an integer linear programming problem. However, such formulation is computationally expensive for designs with large number of flip-flops. In this work, we propose a fast heuristic method to schedule clock skew for reducing peak current. The proposed method is evaluated on ISCAS-89, ITC99 and synthetic benchmark circuits. Results show that the proposed method finds a near-optimal solution within minutes even for the largest benchmark circuits.