Abstract
This paper proposes an efficient VLSI architecture for integer discrete cosine transform (integer DCT) that is used in real time high efficiency video coding (HEVC) applications. The proposed N-point 1D-Integer DCT architecture consists of signed configurable carry save adder tree based multiplier unit. So, the depth of the architecture falls within the bounds of O(log2 N). The proposed 1D architecture is used to perform one N-point or multiple N 2 ; N 4 ; :::2-point Integer DCTs in parallel. The proposed 1D architecture is used to design 2D folded and parallel designs. The performance results show that the proposed architecture gives better performance compared with existing architectures using 45 nm CMOS TSMC library. The proposed 3232-point parallel Integer DCT achieves 59:1% of improvement in worst path delay compared with odd-even decomposition [3] based architecture.