Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium
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Abstract

Presents a novel technique for the design of iterative circuits with concurrent error correction capabilities. The new method is called 'recomputing with partitioning and voting' (RWPV). It uses a combination of hardware and time redundancy to achieve fault tolerance while providing the same error correction capabilities as found in hardware TMR or time redundancy computation. RWPV error correction is obtained with small hardware and time overhead, as compared to over 200% overhead in either hardware or time for TMR or time redundancy.<>
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