Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs

Guillaume Renaud; Marc Margalef-Rovira; Manuel J. Barragan; Salvador Mir

doi:10.1109/VTS.2017.7928951

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2017 IEEE 35th VLSI Test Symposium (VTS)

Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs

Year: 2017, Pages: 1-6

DOI Bookmark: 10.1109/VTS.2017.7928951

Authors

Guillaume Renaud, Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, F-38000, France
Marc Margalef-Rovira, Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, F-38000, France
Manuel J. Barragan, Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, F-38000, France
Salvador Mir, Univ. Grenoble Alpes, CNRS, Grenoble INP, TIMA, F-38000, France

Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs

Authors

Abstract