Simulation of P- and N-MOSFET hot-carrier degradation in CMOS circuits

P.M. Lee; T. Garfinkel; P.K. Ko; C. Hu

doi:10.1109/VTSA.1991.246684

1991 International Symposium on VLSI Technology, Systems, and Applications

Simulation of P- and N-MOSFET hot-carrier degradation in CMOS circuits

Year: 1991, Pages: 191,192,193,194,195

DOI Bookmark: 10.1109/VTSA.1991.246684

Authors

P.M. Lee, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
T. Garfinkel, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
P.K. Ko, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
C. Hu, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

Abstract

A PMOSFET hot-carrier degradation model has been incorporated into the reliability simulator BERT-CAS, enabling prediction of dynamic circuit-level degradation in which both PMOSFET and NMOSFET degradation play a major role. Comparisons are presented which reveal the good fit obtained between measurement and simulation results.<>

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Simulation of P- and N-MOSFET hot-carrier degradation in CMOS circuits

Authors

Abstract

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