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Proceedings
ARITH
ARITH 2020
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2020 IEEE 27th Symposium on Computer Arithmetic (ARITH)
June 7 2020 to June 10 2020
Portland, OR, USA
ISBN: 978-1-7281-7120-3
Table of Contents
[Title page]
Freely available from IEEE.
pp. i-i
[Title page]
Freely available from IEEE.
pp. i-i
[ARITH 2020 Copyright notice]
Freely available from IEEE.
pp. i-i
Table of Contents
Freely available from IEEE.
pp. i-iii
Foreword ARITH 2020
Freely available from IEEE.
pp. i-i
by
Marius Cornea
,
Weiqiang Liu
,
Arnaud Tisserand
ARITH 2020 Committees
Freely available from IEEE.
pp. i-i
ARITH 2020 Committees
Freely available from IEEE.
pp. i-i
ARITH 2020 List Reviewer Page
Freely available from IEEE.
pp. i-i
Sponsors ARITH 2020
Freely available from IEEE.
pp. i-i
Floating–Point Fused Multiply–Add under HUB Format
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pp. 1-8
by
Javier Hormigo
,
Julio Villalba-Moreno
,
Sonia Gonzalez-Navarro
A Correctly-Rounded Fixed-Point-Arithmetic Dot-Product Algorithm
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pp. 9-16
by
Sylvie Boldo
,
Diane Gallois-Wong
,
Thibault Hilaire
Heuristics for the Design of Large Multipliers for FPGAs
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pp. 17-24
by
Andreas Böttcher
,
Keanu Kullmann
,
Martin Kumm
Efficient, arbitrarily high precision hardware logarithmic arithmetic for linear algebra
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pp. 25-32
by
Jeff Johnson
A Novel Method of Modular Multiplication Based on Karatsuba-like Multiplication
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pp. 33-40
by
Zhen Gu
,
Shuguo Li
Alternative Split Functions and Dekker’s Product
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pp. 41-47
by
Stef Graillat
,
Vincent Lefèvre
,
Jean-Michel Muller
Algorithms for Manipulating Quaternions in Floating-Point Arithmetic
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pp. 48-55
by
Mioara Joldeş
,
Jean-Michel Muller
A Hole in the Ladder : Interleaved Variables in Iterative Conditional Branching
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pp. 56-63
by
Yoann Marquer
,
Tania Richmond
Highly Optimized Montgomery Multiplier for SIKE Primes on FPGA
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pp. 64-71
by
Rami Elkhatib
,
Reza Azarderakhsh
,
Mehran Mozaffari-Kermani
Fast, Small, and Area-Time Efficient Architectures for Key-Exchange on Curve25519
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pp. 72-79
by
Mojtaba Bisheh Niasar
,
Rami El Khatib
,
Reza Azarderakhsh
,
Mehran Mozaffari-Kermani
An asymptotically faster version of FV supported on HPR
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pp. 80-87
by
Jean-Claude Bajard
,
Julien Eynard
,
Paulo Martins
,
Leonel Sousa
,
Vincent Zucca
Maximum Delay Models for Parallel-Prefix Adders in the Presence of Threshold Voltage Variations
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pp. 88-95
by
Kleanthis Papachatzopoulos
,
Vassilis Paliouras
Variable Precision 16-Bit Floating-Point Vector Unit for Embedded Processors
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pp. 96-102
by
Alberto Nannarelli
A Framework for Semi-Automatic Precision and Accuracy Analysis for Fast and Rigorous Deep Learning
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pp. 103-110
by
Christoph Lauter
,
Anastasia Volkova
Variable-Radix Coding of the Reals
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pp. 111-116
by
Peter Lindstrom
Automatic Design Space Exploration for an Error Tolerant Application
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pp. 117-120
by
Samuel Coward
,
Theo Drane
,
Yoav Harel
Custom-Precision Mathematical Library Explorations for Code Profiling and Optimization
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pp. 121-124
by
David Defour
,
Pablo de Oliveira Castro
,
Matei Iştoan
,
Eric Petit
SIMD Multi Format Floating-Point Unit on the IBM z15(TM)
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pp. 125-128
by
Stefan Payer
,
Cedric Lichtenau
,
Michael Klein
,
Kerstin Schelm
,
Petra Leber
,
Nicol Hofmann
,
Tina Babinsky
Issues with rounding in the GCC implementation of the ISO 18037:2008 standard fixed-point arithmetic
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pp. 129-132
by
Mantas Mikaitis
Intel Nervana Neural Network Processor-T (NNP-T) Fused Floating Point Many-Term Dot Product
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pp. 133-136
by
Brian Hickmann
,
Jieasheng Chen
,
Michael Rotzin
,
Andrew Yang
,
Maciej Urbanski
,
Sasikanth Avancha
ARITH 2020 Index
Freely available from IEEE.
pp. i-i
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