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Proceedings
ARRAYS
ARRAYS 1988
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Proceedings. International Conference on Systolic Arrays
May 25 1988 to May 27 1988
San Diego, CA, USA
Table of Contents
Proceedings of the International Conference on Systolic Arrays (Cat. No.88CH2603-9)
Freely available from IEEE.
pp. 0_1
Systolic array for 2-D adaptive beamforming
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pp. 1,2,3,4,5,6,7,8,9,10
by
T.V. Vo
,
J. Litva
An efficient systolic array for MVDR beamforming
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pp. 11,12,13,14,15,16,17,18,19,20
by
J.G. McWhirter
,
T.J. Shepherd
Implementation of synthetic aperture radar algorithms on a systolic/cellular architecture
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pp. 21,22,23,24,25,26,27,28,29,30
by
K.W. Przytula
,
J.G. Nash
Efficient feature extractions by uniform structure threshold logic arrays
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pp. 33,34,35,36,37,38,39,40
by
T. Ejima
Architecture of a programmable systolic array
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pp. 41,42,43,44,45,46,47,48,49
by
R. Hughey
,
D.P. Lopresti
Synthesizing optimal family of linear systolic arrays for matrix computations
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pp. 51,52,53,54,55,56,57,58,59,60
by
V.K.P. Kumar
,
Y.-C. Tsai
Theory for systolizing global computational problems
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pp. 61,62,63,64,65,66,67,68,69,70,71
by
W. Liu
,
R.K. Cavin
,
T. Hughes
New architectures for systolic hashing
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pp. 73,74,75,76,77,78,79,80,81,82
by
G. Panneerselvam
,
G.A. Jullien
,
W.C. Miller
Linear systolic array for least-squares estimation
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pp. 83,84,85,86,87,88,89,90,91,92
by
M.-J. Chen
,
K. Yao
A cellular algorithm for straight line extraction
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pp. 93,94,95,96,97,98,99,100,101,102
by
T. De Saint Pierre
,
M. Milgram
A one dimensional systolic array for solving arbitrarily large least mean square problems
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pp. 103,104,105,106,107,108,109,110,111,112
by
N. Torralba
,
J.J. Navarro
Performance evaluation of the HERMES multibit systolic array architecture for low level processing tasks
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pp. 113,114,115,116,117,118,119,120,121,122,123,124
by
N. Bourbakis
,
F. Barlos
On partitioning the Faddeev algorithm
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pp. 125,126,127,128,129,130,131,132,133,134
by
J.H. Moreno
,
T. Lang
Systolic arrays for implementation of order-recursive least-squares adaptive filtering algorithms
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pp. 135,136,137,138,139,140,141,142,143,144
by
F. Ling
A systolic architecture for the symmetric tridiagonal eigenvalue problem
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pp. 145,146,147,148,149,150
by
W. Phillips
,
W. Robertson
Systolic FFT algorithms on Boolean cube networks
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pp. 151,152,153,154,155,156,157,158,159,160,161,162
by
L. Johnson
,
C.-T. Ho
,
M. Jacquemin
,
A. Ruttenberg
Parallel architectures for artificial neural nets
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pp. 163,164,165,166,167,168,169,170,171,172,173,174
by
S.Y. King
Stereo matching of satellite images with transputers
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pp. 175,176,177,178,179,180,181,182
by
K.A. Collins
,
J.B.G. Roberts
The use of linear arrays for image processing
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pp. 183,184,185,186,187,188,189,190,191,192
by
T.J. Fountain
A million transistor systolic array graphics engine
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pp. 193,194,195,196,197,198,199,200,201,202
by
N. Gharachorloo
,
S. Gupta
,
E. Hokenek
,
P. Balasubramanian
,
W. Bogholtz
,
C. Mathieu
,
C. Zoulas
A systolic array with constant I/O bandwidth for the generalized Fourier transform
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pp. 207,208,209,210,211,212,213,214,215,216
by
H. Hellwagner
A massively parallel systolic array processor system
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pp. 217,218,219,220,221,222,223,224,225
by
R.E. Morley
,
T.J. Sullivan
Implementation of array structured maximum likelihood decoders
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pp. 227,228,229,230,231,232,233,234,235,236
by
K.-A. Wen
,
J.-F. Wang
,
J.-Y. Lee
,
M.-Y. Lin
Regular processor arrays for matrix algorithms with pivoting
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pp. 237,238,239,240,241,242,243,244,245,246
by
V.P. Roychowdhury
,
T. Kailath
Systolic algorithms for some scheduling and graph problems
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pp. 247-256
by
O.H. Ibarra
,
T. Jiang
,
J.H. Chang
,
M.A. Palis
A shortperiodic two-dimensional systolic sorting algorithm
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pp. 257,258,259,260,261,262,263,264
by
U. Schwiegelshohn
A block algorithm for the algebraic path problem and its execution on a systolic array
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pp. 265,266,267,268,269,270,271,272,273,274
by
F.J. Nunez
,
M. Valero
The design of a systolic array system for linear state equations
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pp. 275,276,277,278,279,280,281,282,283,284
by
S.-J. Jou
,
C.-W. Jen
,
W.-Z. Shen
Mapping strategy for automatic design of systolic arrays
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pp. 285,286,287,288,289,290,291,292,293,294
by
C.K. Ko
,
O. Wing
Transitive closure on an instruction systolic array
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pp. 295,296,297,298,299,300,301,302,303,304
by
H.-W. Lang
The derivation of regular synchronous circuits
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pp. 305,306,307,308,309,310,311,312,313,314
by
W. Luk
,
G. Jones
Systolic arrays for group explicit methods for solving parabolic partial differential equations
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pp. 315,316,317,318,319,320,321,322,323,324,325,326,327,328,329
by
D.J. Evans
,
G.M. Megson
Formal derivation of systolic arrays-a case study
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pp. 331,332,333,334,335,336,337,338,339,340
by
M. Payer
Parallel algorithms and systolic array designs for RSA cryptosystem
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pp. 341,342,343,344,345,346,347,348,349,350
by
C.N. Zhang
,
H.L. Martin
,
D.Y.Y. Yun
Mapping systolic algorithms into shuffle arrays
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pp. 351,352,353,354,355,356,357,358,359,360
by
W.-T. Lin
A systolic algorithm and architecture for solving sets of linear equations with multi-band coefficient matrix
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pp. 361,362,363,364,365,366,367,368,369,370,371
by
P.F.C. Krekel
,
E.F. Deprettere
Scheduling a system of affine recurrence equations onto a systolic array
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pp. 373,374,375,376,377,378,379,380,381,382
by
Y. Yaacoby
,
P.R. Cappello
SYSTARS: A CAD tool for the synthesis and analysis of VLSI systolic/wavefront arrays
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pp. 383,384,385,386,387,388,389,390,391
by
E.T.L. Omtzigt
Time optimal linear schedules for algorithms with uniform dependencies
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pp. 393,394,395,396,397,398,399,400,401,402
by
W. Shang
,
J.A.B. Fortes
Broadcast removal in systolic algorithms
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pp. 403,404,405,406,407,408,409,410,411,412
by
Y. Wong
,
J.-M. Delosme
HIFI: a functional design system for VLSI processing arrays
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pp. 413,414,415,416,417,418,419,420,421,422,423,424,425,426,427,428,429,430,431,432,433,434,435,436,437,438,439,440,441,442,443,444,445,446,447,448,449,450,451,452
by
J. Annevelink
,
P. Dewilde
A systematic approach to the design of modular systolic arrays
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pp. 453,454,455,456,457,458,459,460,461,462
by
P. Bertolazzi
,
C. Guerra
,
S. Salza
A pragmatic approach to systolic design
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pp. 463,464,465,466,467,468,469,470,471,472
by
S. Manohar
,
G. Baudet
Uniformization of linear recurrence equations: a step toward the automatic synthesis of systolic arrays
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pp. 473,474,475,476,477,478,479,480,481,482
by
V. Van Dongen
,
P. Quinton
A linear algebraic model of algorithmic-based fault tolerance
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pp. 483,484,485,486,487,488,489,490,491,492,493
by
C.J. Anfinson
,
F.T. Luk
New conditions for testability of two-dimensional bilateral arrays
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pp. 495,496,497,498,499,500,501,502,503,504
by
D. Sciuto
,
F. Lombardi
On the design of easily testable and reconfigurable systolic arrays
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pp. 505,506,507,508,509,510,511,512,513,514
by
J.H. Kim
The ASP, a fault tolerant VLSI/ULSI/WSI associative string processor for cost-effective systolic processing
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pp. 515,516,517,518,519,520,521,522,523,524
by
R.M. Lea
A parallel video signal processor, based on overlap save techniques
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pp. 525,526,527,528,529,530,531,532,533,534
by
T. Nishitani
Cellular array processor CAP and applications
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pp. 535,536,537,538,539,540,541,542,543,544
by
M. Ishi
,
H. Sato
,
K. Murakami
,
M. Ikesaka
,
H. Ishihata
A probabilistic model for clock skew
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pp. 545,546,547,548,549,550,551,552,553,554
by
S.D. Kugelmass
,
K. Steiglitz
Interconnection complexity study for a piggy back WSHP GaAs systolic processor
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pp. 555,556,557,558,559,560,561,562,563,564
by
R. Philhower
,
J.F. McDonald
Policies for fault-tolerance through mixed space- and time-redundancy in semi-systolic FFT arrays
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pp. 565,566,567,568,569,570,571,572,573,574,575,576
by
A. Antola
,
R. Negrini
,
M.G. Sami
,
N. Scarabottolo
A systolic array for fault tolerant digital signal processing using a residue number system approach
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pp. 577,578,579,580,581,582,583,584,585,586
by
S. Bandyopadhyay
,
G.A. Jullien
,
A. Sengupta
A systolic integrated circuit integer divider
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pp. 587,588,589,590,591
by
J.A. Eldon
An efficient asynchronous multiplier
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pp. 593,594,595,596,597,598,599
by
R.M. Goodman
,
A.J. McAuley
Homogeneous multicomputer type DSP system NOVI for parallel signal processing
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pp. 601,602,603,604,605,606,607,608,609,610
by
N. Ohta
,
T. Fujii
,
Y. Kanayama
,
S. Ono
A multiprocessor system utilizing enhanced DSPs for image processing
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pp. 611,612,613,614,615,616,617,618,619,620
by
H. Ueda
,
K. Kato
,
H. Matsushima
,
K. Kaneko
,
M. Ejiri
Architecture of SIPS, a real time image processing system
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pp. 621,622,623,624,625,626,627,628,629,630
by
A. Hasebe
,
J. Yonemitsu
,
R. Kato
,
N. Ito
,
H. Fujita
A reconfigurable VLSI array for reliability and yield enhancement
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pp. 631,632,633,634,635,636,637,638,639,640,641,642
by
S.P. Popli
,
M.A. Bayoumi
A systolic square root information Kalman filter
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pp. 643,644,645,646,647,648,649,650,651,652
by
F.M.F. Gaston
,
G.W. Irwin
Bit-level systolic arrays for IIR filtering
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pp. 653,654,655,656,657,658,659,660,661,662,663
by
S.C. Knowles
,
R.F. Woods
,
J.G. McWhirter
,
J.V. McCanny
A high level synthesis tool for systolic designs
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pp. 665,666,667,668,669,670,671,672,673
by
P.-P. Hou
,
R.M. Owens
,
M.J. Irwin
Systolic array system for vector quantization using transformed sub-band coding
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pp. 675,676,677,678,679,680,681,682,683,684
by
M. Yan
,
J.V. McCanny
,
H.A. Kaouri
A systematic approach to bit recursive systolic array design
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pp. 685,686,687,688,689,690,691,692,693,694
by
K.R. Liu
,
K. Yao
Systolic communication
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pp. 695,696,697,698,699,700,701,702,703
by
H.T. Kung
Showing 67 out of 67