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ASAP 2010 - 21st IEEE International Conference on Application-specific Systems, Architectures and Processors

July 7 2010 to July 9 2010

Rennes

Table of Contents

Convergence of design and fabrication technologies, a key enabler for HW-SW integrationFreely available from IEEE.pp. 3-3
by Ahmed A. Jerraya
The light at the end of the CMOS tunnelFreely available from IEEE.pp. 4-9
by Sani R. Nassif
Session 1: Mapping for multi-core architectures [breaker page]Freely available from IEEE.pp. 1-1
Dynamic code mapping for limited local memory systemsFull-text access may be available. Sign in or learn about subscription options.pp. 13-20
by Seung chul Jung, Aviral Shrivastava, Ke Bai
Design of an Automatic Target Recognition algorithm on the IBM Cell Broadband EngineFull-text access may be available. Sign in or learn about subscription options.pp. 21-28
by Weijia Che, Karam S. Chatha
Highly efficient mapping of the Smith-Waterman algorithm on CUDA-compatible GPUsFull-text access may be available. Sign in or learn about subscription options.pp. 29-36
by Keisuke Dohi, Khaled Benkridt, Cheng Ling, Tsuyoshi Hamada, Yuichiro Shibata
Session 2: Design space exploration [breaker page]Freely available from IEEE.pp. 1-1
ImpEDE: A multidimensional design-space exploration framework for biomedical-implant processorsFull-text access may be available. Sign in or learn about subscription options.pp. 39-46
by Dhara Dave, Christos Strydis, Georgi N. Gaydadjiev
Design space exploration of parametric pipelined designsFull-text access may be available. Sign in or learn about subscription options.pp. 47-54
by Adrien Le Masle, Wayne Luk
Design space exploration for an embedded processor with flexible datapath interconnectFull-text access may be available. Sign in or learn about subscription options.pp. 55-62
by Tung Thanh Hoang, Ulf Jälmbrant, Erik der Hagopian, Kasyab P. Subramaniyan, Magnus Själander, Per Larsson-Edefors
Session 3: Systems-on-Chip and Networks-on-Chip [breaker page]Freely available from IEEE.pp. 1-1
Using shared library interposing for transparent application acceleration in systems with heterogeneous hardware acceleratorsFull-text access may be available. Sign in or learn about subscription options.pp. 65-72
by Tobias Beisel, Manuel Niekamp, Christian Plessl
Enhancing performance of network-on-chip architectures with millimeter-wave wireless interconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 73-80
by Sujay Deb, Amlan Ganguly, Kevin Chang, Partha Pande, Benjamin Beizer, Deuk Heo
A Bayesian network-based framework with Constraint Satisfaction Problem (CSP) formulations for FPGA system designFull-text access may be available. Sign in or learn about subscription options.pp. 81-88
by Amelia W. Azman, Abbas Bigdeli, Yasir Mohd-Mustafah, Morteza Biglari-Abhari, Brian C. Lovell
An optimized NoC architecture for accelerating TSP kernels in breakpoint median problemFull-text access may be available. Sign in or learn about subscription options.pp. 89-96
by Turbo Majumder, Souradip Sarkar, Partha Pande, Ananth Kalyanaraman
Session 4: Formal methods [breaker page]Freely available from IEEE.pp. 1-1
A formal specification of fault-tolerance in prospecting asteroid mission with Reactive Autonomie Systems FrameworkFull-text access may be available. Sign in or learn about subscription options.pp. 99-106
by Heng Kuang, Olga Ormandjieva, Stan Klasa, Jamal Bentahar
Comparing the robustness of fault-tolerant enhancements when applied to lookup tables and random logic for nano-computingFull-text access may be available. Sign in or learn about subscription options.pp. 107-114
by Yocheved Dotan, Orgad Chen, Gil Katz
Dependability analysis of a countermeasure against fault attacks by means of laser shots onto a SRAM-based FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 115-122
by G. Canivet, P. Maistri, R. Leveugle, F. Valette, J. Clédière, M. Renaudin
Session 5: Design and programming of array architectures [breaker page]Freely available from IEEE.pp. 1-1
Modeling and synthesis of communication subsystems for loop accelerator pipelinesFull-text access may be available. Sign in or learn about subscription options.pp. 125-132
by Hritam Dutta, Frank Hannig, Moritz Schmid, Joachim Keinert
Design of throughput-optimized arrays from recurrence abstractionsFull-text access may be available. Sign in or learn about subscription options.pp. 133-140
by Arpith C. Jacob, Jeremy D. Buhler, Roger D. Chamberlain
A C++-embedded Domain-Specific Language for programming the MORA soft processor arrayFull-text access may be available. Sign in or learn about subscription options.pp. 141-148
by W. Vanderbauwhede, M. Margala, S. R. Chalamalasetti, S. Purohit
Session 6: Application-specific processors [breaker page]Freely available from IEEE.pp. 1-1
A forwarding-sensitive instruction scheduling approach to reduce register file constraints in VLIW architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 151-158
by Guillermo Payá-Vayá, Javier Martín-Langerwerf, Holger Blume, Peter Pirsch
Dual-purpose custom instruction identification algorithm based on Particle Swarm OptimizationFull-text access may be available. Sign in or learn about subscription options.pp. 159-166
by Mehdi Kamal, Neda Kazemian Amiri, Arezoo Kamran, Seyyed Alireza Hoseini, Masoud Dehyadegari, Hamid Noori
Combined scheduling and instruction selection for processors with reconfigurable cell fabricFull-text access may be available. Sign in or learn about subscription options.pp. 167-174
by Antoine Floch, Christophe Wolinski, Krzysztof Kuchcinski
Completeness of automatically generated instruction selectorsFull-text access may be available. Sign in or learn about subscription options.pp. 175-182
by Florian Brandner
Session 7: Computer arithmetics and cryptography [breaker page]Freely available from IEEE.pp. 1-1
Implementation of binary edwards curves for very-constrained devicesFull-text access may be available. Sign in or learn about subscription options.pp. 185-191
by Ünal Kocabaş, Junfeng Fan, Ingrid Verbauwhede
Elliptic Curve point multiplication on GPUsFull-text access may be available. Sign in or learn about subscription options.pp. 192-199
by Samuel Antão, Jean-Claude Bajard, Leonel Sousa
Newton-Raphson algorithms for floating-point division using an FMAFull-text access may be available. Sign in or learn about subscription options.pp. 200-207
by Nicolas Louvet, Jean-Michel Muller, Adrien Panhaleux
An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbersFull-text access may be available. Sign in or learn about subscription options.pp. 208-215
by David B. Thomas, Wayne Luk
Automatic generation of polynomial-based hardware architectures for function evaluationFull-text access may be available. Sign in or learn about subscription options.pp. 216-222
by Florent de Dinechin, Mioara Joldes, Bogdan Pasca
Session 8: Application-specific architectures [breaker page]Freely available from IEEE.pp. 1-1
A fully-overlapped multi-mode QC-LDPC decoder architecture for mobile WiMAX applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 225-232
by Bo Xiang, Dan Bao, Shuangqu Huang, Xiaoyang Zeng
High parallel variation Banyan network based permutation network for reconfigurable LDPC decoderFull-text access may be available. Sign in or learn about subscription options.pp. 233-238
by Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Fumiaki Maehara, Satoshi Goto
A high efficient memory architecture for H.264/AVC motion compensationFull-text access may be available. Sign in or learn about subscription options.pp. 239-245
by Chunshu Li, Kai Huang, Xiaolang Yan, Jiong Feng, De Ma, Haitong Ge
FPGA-based lossless compressors of floating-point data streams to enhance memory bandwidthFull-text access may be available. Sign in or learn about subscription options.pp. 246-253
by Kazuya Katahira, Kentaro Sano, Satoru Yamamoto
Session 9: Power-aware architectures [breaker page]Freely available from IEEE.pp. 1-1
Power dissipation challenges in multicore floating-point unitsFull-text access may be available. Sign in or learn about subscription options.pp. 257-264
by Wei Liu, Alberto Nannarelli
On energy efficiency of reconfigurable systems with run-time partial reconfigurationFull-text access may be available. Sign in or learn about subscription options.pp. 265-272
by Shaoshan Liu, Richard Neil Pittman, Alessandro Forin, Jean-Luc Gaudiot
A GALS FFT processor with clock modulation for low-EMI applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 273-278
by Xin Fan, Milos Krstic, Christoph Wolf, Eckhard Grass
Hardware-assisted middleware: Acceleration of garbage collection operationsFull-text access may be available. Sign in or learn about subscription options.pp. 281-284
by Jie Tang, Shaoshan Liu, Zhimin Gu, Xiao-Feng Li, Jean-Luc Gaudiot
Flexible hardware/software co-design for scalable elliptic curve cryptography for low-resource applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 285-288
by M. N. Hassan, M. Benaissa, A. Kanakis
An efficient computation model for coarse grained reconfigurable architectures and its applications to a reconfigurable computerFull-text access may be available. Sign in or learn about subscription options.pp. 289-292
by Oguzhan Atak, Abdullah Atalar
Potential of using block floating point arithmetic in ASIP-based GNSS-receiversFull-text access may be available. Sign in or learn about subscription options.pp. 293-296
by E. Tasdemir, G. Kappen, T. G. Noll
Area optimized H.264 Intra prediction architecture for 1080p HD resolutionFull-text access may be available. Sign in or learn about subscription options.pp. 297-300
by Jimit Shah, K. S. Raghunandan, Kuruvilla Varghese
Memoryless RNS-to-binary converters for the {2n+1 - 1, 2n, 2n - 1} moduli setFull-text access may be available. Sign in or learn about subscription options.pp. 301-304
by Kazeem Alagbe Gbolagade, George Razvan Voicu, Sorin Dan Cotofana
A pipelined camellia architecture for compact hardware implementationFull-text access may be available. Sign in or learn about subscription options.pp. 305-308
by Elif Bilge Kavun, Tolga Yalcin
General-purpose FPGA platform for efficient encryption and hashingFull-text access may be available. Sign in or learn about subscription options.pp. 309-312
by Jakub Szefer, Yu-Yuan Chen, Ruby B. Lee
A compact FPGA-based architecture for elliptic curve cryptography over prime fieldsFull-text access may be available. Sign in or learn about subscription options.pp. 313-316
by Jo Vliegen, Nele Mentens, Jan Genoe, An Braeken, Serge Kubera, Abdellah Touhafi, Ingrid Verbauwhede
Implementing decimal floating-point arithmetic through binary: Some suggestionsFull-text access may be available. Sign in or learn about subscription options.pp. 317-320
by Nicolas Brisebarre, Nicolas Louvet, Érik Martin-Dorel, Jean-Michel Muller, Adrien Panhaleux, Miloš D. Ercegovac
A New approach in on-line task scheduling for reconfigurable computing systemsFull-text access may be available. Sign in or learn about subscription options.pp. 321-324
by Maisam Mansub Bassiri, Hadi Shahriar Shahhoseini
Exploring algorithmic trading in reconfigurable hardwareFull-text access may be available. Sign in or learn about subscription options.pp. 325-328
by Stephen Wray, Wayne Luk, Peter Pietzuch
Optimizing DDR-SDRAM communications at C-level for automatically-generated hardware accelerators an experience with the Altera C2H HLS toolFull-text access may be available. Sign in or learn about subscription options.pp. 329-332
by Christophe Alias, Alain Darte, Alexandra Plesco
Deadlock-avoidance for streaming applications with split-join structure: Two case studiesFull-text access may be available. Sign in or learn about subscription options.pp. 333-336
by Peng Li, Kunal Agrawal, Jeremy Buhler, Roger D. Chamberlain, Joseph M. Lancaster
Customizing controller instruction sets for application-specific architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 337-340
by Jian Li, David Dickin, Lesley Shannon
Loop transformations for interface-based hierarchies IN SDF graphsFull-text access may be available. Sign in or learn about subscription options.pp. 341-344
by Jonathan Piat, Shuvra S. Bhattacharyya, Michael Raulet
Code generation for hardware accelerated AESFull-text access may be available. Sign in or learn about subscription options.pp. 345-348
by Raymond Manley, Paul Magrath, David Gregg
Function flattening for lease-based, information-leak-free systemsFull-text access may be available. Sign in or learn about subscription options.pp. 349-352
by Xun Li, Mohit Tiwari, Timothy Sherwood, Frederic T. Chong
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