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Asia and South Pacific Design Automation Conference

Jan. 18 1999 to Jan. 21 1999

Wanchai, Hong Kong

ISBN: 0-7803-5012-X

Table of Contents

Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198)Freely available from IEEE.pp. i-i
Organizing CommitteeFreely available from IEEE.pp. iii
International Advisory CommitteeFreely available from IEEE.pp. vi
Steering CommitteeFreely available from IEEE.pp. vii
Welcome to ASP-DAC'99Freely available from IEEE.pp. xii
Welcome to ASP-DAC'99 ExhibitionFreely available from IEEE.pp. xiii
Invitation to ASP-DAC 2000Freely available from IEEE.pp. xiv
Technical Program CommitteeFreely available from IEEE.pp. xv
Best Paper Award CandidatesFreely available from IEEE.pp. xvi
University LSI Design Contest CommitteeFreely available from IEEE.pp. xvii
University LSI Design Contest SummaryFreely available from IEEE.pp. xviii
Session 2A: Analog CAD
Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 1
by Xiang-Dong Tan, C.-J. Richard Shi
Session 2A: Analog CAD
Symmetry Detection for Automatic Analog-Layout RecyclingFull-text access may be available. Sign in or learn about subscription options.pp. 5
by Youcef Bourai, C.-J. Richard Shi
Session 2A: Analog CAD
An SA-Based Nonlinear Function Synthesizer for Linear Analog Integrated CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 9
by Huazhong Yang, Rong Luo, Hui Wang, Runsheng Liu
Session 2B: Physical Design 1 - Floorplanning
Relaxed Simulated Tempering for VLSI Floorplan DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 13
by Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong
Session 2B: Physical Design 1 - Floorplanning
Slicing Floorplans with Boundary ConstraintFull-text access may be available. Sign in or learn about subscription options.pp. 17
by F. Y. Young, D. F. Wong
Session 2B: Physical Design 1 - Floorplanning
Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro CellsFull-text access may be available. Sign in or learn about subscription options.pp. 21
by Xiaohai Wu, Changge Qiao, Xianlong Hong
Session 2C: Design Contest
An 8b 52MHz Double-Channel CMOS A/D Converter for High-Speed Data CommunicationsFull-text access may be available. Sign in or learn about subscription options.pp. 25
by Ju-Hyung Kim, Sung-Wook Hwang, Seung-Hoon Lee, Yong Jee
Session 2C: Design Contest
A 10b 50 MHz CMOS A/D Converter for High-Speed Video ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 29
by Byeong-Lyeol Jeon, Kang-Jin Lee, Seung-Hoon Lee, Sang-Won Yoon
Session 2C: Design Contest
The Design of Delay Insensitive Asynchronous 16-bit MicroprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 33
by Byung-Soo Choi, Dong-Wook Lee, Dong-Ik Lee
Session 2C: Design Contest
An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator SelectionFull-text access may be available. Sign in or learn about subscription options.pp. 37
by Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta
Session 2C: Design Contest
Motion Estimator LSI for MPEG2 High Level StandardFull-text access may be available. Sign in or learn about subscription options.pp. 41
by Li Jiang, Dongju Li, Shintaro Haba, Chawalit Honsawek, Hiroaki Kunieda
Session 2C: Design Contest
A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGCFull-text access may be available. Sign in or learn about subscription options.pp. 45
by Jin-Kug Lee, Dong-Young Chang, Geun-Soon Kang, Seung-Hoon Lee
Session 2C: Design Contest
16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular TelephonyFull-text access may be available. Sign in or learn about subscription options.pp. 49
by Tae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim, Sang Lin Byun, Bae Sung Kwon, Beomsup Kim
Session 3A: Circuit Simulation 1
Reduced-Order Modelling of Time-Varying SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 53
by Jaijeet Roychowdhury
Session 3A: Circuit Simulation 1
Analysing Forced Oscillators with Multiple Time ScalesFull-text access may be available. Sign in or learn about subscription options.pp. 57
by Onuttom Narayan, Jaijeet Roychowdhury
Session 3A: Circuit Simulation 1
Waveform Relaxation of Linear Integral-Differential Equations for Circuit SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 61
by Yao-Lin Jiang, Omar Wing
Session 3A: Circuit Simulation 1
A New Technique to Exploit Frequency Domain Latency in Harmonic Balance SimulatorsFull-text access may be available. Sign in or learn about subscription options.pp. 65
by M. M. Gourary, S. G. Rusakov, S. L. Ulyanov, M. M. Zharov, K. K. Gullapalli, B. J. Mulvaney
Session 3B: Physical Design 2 - Partitioning
An Efficient Two-Level Partitioning Algorithm for VLSI CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 69
by Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho
Session 3B: Physical Design 2 - Partitioning
An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket StructuresFull-text access may be available. Sign in or learn about subscription options.pp. 73
by C. K. Eem, J. W. Chong
Session 3B: Physical Design 2 - Partitioning
A Clustering Based Linear Ordering Algorithm for K-Way Spectral PartitioningFull-text access may be available. Sign in or learn about subscription options.pp. 77
by Shiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, TingTing Hwang
Session 3B: Physical Design 2 - Partitioning
Faster and Better Spectral Algorithms for Multi-Way PartitioningFull-text access may be available. Sign in or learn about subscription options.pp. 81
by Jan-Yang Chang, Yu-Chen Liu, Ting-Chi Wang
Session 4A: Circuit Simulation 2
VCO Jitter Simulation and Its Comparison With MeasurementFull-text access may be available. Sign in or learn about subscription options.pp. 85
by Masayuki Takahashi, Kimihiro Ogawa, Kenneth S. Kundert
Session 4A: Circuit Simulation 2
Enhancing the Efficiency of Reduction of Large RC networks By Pole Analysis via Congruence TransformationsFull-text access may be available. Sign in or learn about subscription options.pp. 89
by Zheng Hui, Zhang Wenjun, Tian Lilin, Yang Zhilian
Session 4A: Circuit Simulation 2
The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect CapacitanceFull-text access may be available. Sign in or learn about subscription options.pp. 93
by Jinsong Hou, Zeyi Wang, Xianlong Hong
Session 4B: Physical Design 3 - Interconnection
Interconnect Delay Estimation Models for Synthesis and Design PlanningFull-text access may be available. Sign in or learn about subscription options.pp. 97
by Jason Cong, David Zhigang Pan
Session 4B: Physical Design 3 - Interconnection
An Analytical Delay Model for SRAM-Based FPGA InterconnectionsFull-text access may be available. Sign in or learn about subscription options.pp. 101
by Zhou Feng, Huang Zhijun, Tong Jiarong, Tang Pushan
Session 4B: Physical Design 3 - Interconnection
Timing-Driven Bipartitioning with Replication Using Iterative Quadratic ProgrammingFull-text access may be available. Sign in or learn about subscription options.pp. 105
by Shihliang Ou, Massoud Pedram
Session 4B: Physical Design 3 - Interconnection
An Integrated Battery-Hardware Model for Portable ElectronicsFull-text access may be available. Sign in or learn about subscription options.pp. 109
by Massoud Pedram, Chi-Ying Tsui, Qing Wu
Session 6A: Circuit 1 - Low-power/High-speed
Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIsFull-text access may be available. Sign in or learn about subscription options.pp. 113
by Shin-ichiro Mutoh, Satoshi Shigematsu, Yoshinori Gotoh, Shinsuke Konaka
Session 6A: Circuit 1 - Low-power/High-speed
A New Single-Clock Flip-Clop for Half-Swing ClockingFull-text access may be available. Sign in or learn about subscription options.pp. 117
by Young-Su Kwon, Bong-il Park, In-Cheol Park, Chong-Min Kyung
Session 6A: Circuit 1 - Low-power/High-speed
Optimal Evaluation Clocking of Self-Resetting Domino PipelinesFull-text access may be available. Sign in or learn about subscription options.pp. 121
by Kenneth Y. Yun, Ayoob E. Dooply
Session 6A: Circuit 1 - Low-power/High-speed
Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay InsertionFull-text access may be available. Sign in or learn about subscription options.pp. 125
by Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani
Session 6B: Physical Design 4 - Analog, Noise
A Performance-Driven I/O Pin Routing AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 129
by Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arunabha Sen
Session 6B: Physical Design 4 - Analog, Noise
An Automatic Router for the Pin Grid Array PackageFull-text access may be available. Sign in or learn about subscription options.pp. 133
by Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai
Session 6B: Physical Design 4 - Analog, Noise
Crosstalk Reduction by Transistor SizingFull-text access may be available. Sign in or learn about subscription options.pp. 137
by Tong Xiao, Malgorzata Marek-Sadowska
Session 6B: Physical Design 4 - Analog, Noise
A Technology-Independent Methodology of Placement Generation for Analog CircuitFull-text access may be available. Sign in or learn about subscription options.pp. 141
by Wai-chee Wong, Philip C. H. Chan, Wai-on Law
Session 6D: Poster Session
Technnology Mapping for Low PowerFull-text access may be available. Sign in or learn about subscription options.pp. 145
by Chingwei Yeh, Chin-Chao Chang, Jinn-Shyan Wang
Session 6D: Poster Session
An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI RoutingFull-text access may be available. Sign in or learn about subscription options.pp. 149
by Maolin Tang, Kamran Eshraghian, Hon Nin Cheung
Session 6D: Poster Session
Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 153
by Nagu R. Dhanwada, Adrian Nunez-Aldana, Ranga Vemuri
Session 6D: Poster Session
Node Sampling Technique to Speed Up Probability-Based Power Estimation MethodsFull-text access may be available. Sign in or learn about subscription options.pp. 157
by Hoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung
Session 6D: Poster Session
Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing ApproachFull-text access may be available. Sign in or learn about subscription options.pp. 161
by Hidehisa Nagano, Takayuki Suyama, Akira Nagoya
Session 6D: Poster Session
A New Numerical Method for Transient Noise Analysis of Nonlinear CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 165
by M. M. Gourary, S. G. Rusakov, S. L. Ulyanov, M. M. Zharov, B. J. Mulvaney
Session 6D: Poster Session
Low Power CMOS Off-Chip Drivers with Slew-rate DifferenceFull-text access may be available. Sign in or learn about subscription options.pp. 169
by Rung-Bin Lin, Jinq-Chang Chen
Session 6D: Poster Session
Benchmark Circuits Improve the Quality of a Standard Cell LibraryFull-text access may be available. Sign in or learn about subscription options.pp. 173
by Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai
Session 6D: Poster Session
Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction ExecutionFull-text access may be available. Sign in or learn about subscription options.pp. 177
by Takashi Takenaka, Junji Kitamichi, Teruo Higashino, Kenichi Taniguchi
Session 6D: Poster Session
Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-PairFull-text access may be available. Sign in or learn about subscription options.pp. 181
by Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide
Session 6D: Poster Session
Hazard-Free Synthesis and Decomposition of Asynchronous CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 185
by Ren-Der Chen, Jer Min Jou, Yeu-Horng Shiau
Session 6D: Poster Session
Hierarchical Floorplan Design on the InternetFull-text access may be available. Sign in or learn about subscription options.pp. 189
by Jiann-Horng Lin, Jing-Yang Jou, Hui-Ru Jiang
Session 6D: Poster Session
A Scheduling Method for Synchronous Communication in the Bach Hardware CompilerFull-text access may be available. Sign in or learn about subscription options.pp. 193
by Ryoji Sakurai, Mizuki Takahashi, Andrew Kay, Akihisa Yamada, Tetsuya Fujimoto, Takashi Kambe
Session 7A: Circuit 2 - Multmedia chip designs
Electronics Development of Silicon Microdisplay for Virtual Reality ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 197
by P. W. Cheng, H. C. Huang
Session 7A: Circuit 2 - Multmedia chip designs
High-Speed and Low-Power Real-Time Programmable Video Multi-Processor for MPEG-2 Multimedia Chip on 0.6μm TLM CMOS TechnologyFull-text access may be available. Sign in or learn about subscription options.pp. 201
by Seung-Min Lee, Jin-Hong Chung, M. M.-O. Lee
Session 7A: Circuit 2 - Multmedia chip designs
A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet TransformFull-text access may be available. Sign in or learn about subscription options.pp. 205
by Jer Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Ming-Shiang Liang
Session 7A: Circuit 2 - Multmedia chip designs
A New Pipelined Architecture for Fuzzy Color CorrectionFull-text access may be available. Sign in or learn about subscription options.pp. 209
by Jer Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau
Session 7B: Physical Design 5 - Special Topics
Watermarking Layout TopologiesFull-text access may be available. Sign in or learn about subscription options.pp. 213
by Edoardo Charbon, Ilhami Torunoglu
Session 7B: Physical Design 5 - Special Topics
Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay ModelFull-text access may be available. Sign in or learn about subscription options.pp. 217
by Youxin Gao, D. F. Wong
Session 7B: Physical Design 5 - Special Topics
New Multilevel and Hierarchical Algorithms for Layout Density ControlFull-text access may be available. Sign in or learn about subscription options.pp. 221
by Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky
Session 7B: Physical Design 5 - Special Topics
Function Smoothing with Applications to VLSI LayoutFull-text access may be available. Sign in or learn about subscription options.pp. 225
by Ross Baldick, Andrew B. Kahng, Andrew Kennings, Igor L. Markov
Session 8A: Timing analysis
Layout-based Logic Decomposition for Timing OptimizationFull-text access may be available. Sign in or learn about subscription options.pp. 229
by Yun-Yin Lian, Youn-Long Lin
Session 8A: Timing analysis
Timing Optimization of Logic Network Using Gate DuplicationFull-text access may be available. Sign in or learn about subscription options.pp. 233
by Chun-hong Chen, Chi-ying Tsui
Session 8A: Timing analysis
Model Order Reduction of Large Circuits Using Balanced TruncationFull-text access may be available. Sign in or learn about subscription options.pp. 237
by Payam Rabiei, Massoud Pedram
Session 8B: Physical Design 6 - Placement & Route
Optimization of Linear Placements for Wirelength Minimization with Free SitesFull-text access may be available. Sign in or learn about subscription options.pp. 241
by Andrew B. Kahng, Paul Tucker, Alex Zelikovsky
Session 8B: Physical Design 6 - Placement & Route
A New Global Routing Algorithm Independent Of Net OrderingFull-text access may be available. Sign in or learn about subscription options.pp. 245
by Haiyun Bao, Xianlong Hong, Yici Cai
Supplement to the Proceeding of Asia and South Pacific Design Automation Conference 1999Full-text access may be available. Sign in or learn about subscription options.pp. 2
Session 8B: Physical Design 6 - Placement & Route
A Timing-Driven Block Placer Based on Sequence Pair ModelFull-text access may be available. Sign in or learn about subscription options.pp. 249
by Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai
EDA Roadmap and Future VLSI Design Technology EnhancementFull-text access may be available. Sign in or learn about subscription options.pp. 3-3
by T. Hiwatashi
Roadmap organization and activities in JapanFull-text access may be available. Sign in or learn about subscription options.pp. 4 suppl.
by Y. Furui
Session 8B: Physical Design 6 - Placement & Route
Recent Advances in Asynchronous Design MethodologiesFull-text access may be available. Sign in or learn about subscription options.pp. 253
by Kenneth Y. Yun
EDA Roadmap in JapanFull-text access may be available. Sign in or learn about subscription options.pp. 5 suppl.
by T. Hiwatashi
Session 10A: Circuit 3 - Analog & Mixed Circuit
Universal Switched-Current Integrator Blocks for SI Filter DesignFull-text access may be available. Sign in or learn about subscription options.pp. 261
by Jack L. Chan, Steve S. Chung
A US/Japan comparison of design/EDA capabilitiesFull-text access may be available. Sign in or learn about subscription options.pp. 6 suppl.
by H. Mayumi
Session 10A: Circuit 3 - Analog & Mixed Circuit
An On-Chip Automatic Tuning Circuit using Integration Level ApproximationFull-text access may be available. Sign in or learn about subscription options.pp. 265
by Lee Sung-Dae, Jang Myung-Jun, Leex Won-Hyo
VCDS: virtual core based design systemFull-text access may be available. Sign in or learn about subscription options.pp. 7 suppl.
by M. Muraoka
Embedded tutorial: hardware/software codesignFull-text access may be available. Sign in or learn about subscription options.pp. 8 suppl.
by M. Imai
Session 10A: Circuit 3 - Analog & Mixed Circuit
A High Speed and Low Power Phase-Frequency Detector and Charge - pumpFull-text access may be available. Sign in or learn about subscription options.pp. 269
by Won - Hyo Lee, Jun - Dong Cho, Sung - Dae Lee
Microprocessor technologies for the 21st centuryFull-text access may be available. Sign in or learn about subscription options.pp. 9 suppl.-9 suppl.
by R. Yung
Session 10A: Circuit 3 - Analog & Mixed Circuit
A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGCFull-text access may be available. Sign in or learn about subscription options.pp. 273
by Jin-Kug Lee, Dong-Young Chang, Geun-Soon Kang, Seung-Hoon Lee
Session 10B: Testing 1
Data Path Synthesis for BIST with Low Area OverheadFull-text access may be available. Sign in or learn about subscription options.pp. 275
by Xiaowei Li, Paul Y. S. Cheung
Package market segments and design challengesFull-text access may be available. Sign in or learn about subscription options.pp. 10 suppl.-10 suppl.
by R. Bracken
Session 10B: Testing 1
Testing Interconnects of Dynamic Reconfigurable FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 279
by Chi-Feng Wu, Cheng-Wen Wu
Electrical design and design automation for packagingFull-text access may be available. Sign in or learn about subscription options.pp. 11 suppl.
by D. Becker
Session 10B: Testing 1
Diagnosing Single Faults for Interconnects in SRAM Based FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 283
by Yinlei Yu, Jian Xu, Wei Kang Huang, Fabrizio Lombardi
Thermal/mechanical design and design automation for packagingFull-text access may be available. Sign in or learn about subscription options.pp. 12 suppl.
by R. Mahajan
Session 10B: Testing 1
An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 287
by Hafijur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya
Chip-package codesign-challenges and directionsFull-text access may be available. Sign in or learn about subscription options.pp. 13 suppl.
by P. Franzon
Session 11A: Power Estimation/Low-power
A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit PartitionFull-text access may be available. Sign in or learn about subscription options.pp. 291
by Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi
Design re-use: where is the productivity going to come from?Full-text access may be available. Sign in or learn about subscription options.pp. 14 suppl.-14 suppl.
by J. Ahuja
Session 11A: Power Estimation/Low-power
Estimation of Peak Current through CMOS VLSI Circuit Supply LinesFull-text access may be available. Sign in or learn about subscription options.pp. 295
by Toshio Murayama, Kimihiro Ogawa, Haruhiko Yamaguchi
Session 11A: Power Estimation/Low-power
Power Consumption in XOR-Based CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 299
by Yibin Ye, Kaushik Roy, Rolf Drechsler
Session 11A: Power Estimation/Low-power
Exploiting Don't Caers During Data Sequencing using Genetic AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 303
by Rolf Drechsler, Nicole Drechsler
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