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Proceedings of 1998 Asia and South Pacific Design Automation Conference

Feb. 13 1998 to Feb. 13 1998

Yokohama, Japan

Table of Contents

Proceedings of 1998 Asia and South Pacific Design Automation ConferenceFreely available from IEEE.pp. i
High-speed GaAs MESFET digital IC design for optical communication systemsFull-text access may be available. Sign in or learn about subscription options.pp. 1,2,3,4,5
by K. Sano, K. Narahara, K. Murata, T. Otsuji, K. Onodera
Design and experimental results of a 2V-operation single-chip GaAs T/R-MMIC front-end for 1.9-GHz personal communicationsFull-text access may be available. Sign in or learn about subscription options.pp. 7,8,9,10,11,12
by K. Yamamoto, T. Moriwaki, Y. Yoshii, T. Fujii, J. Otsuji, Y. Sasaki, Y. Miyazaki, K. Nishitani
A simple architecture of low voltage GHz BiCMOS four-quadrant analogue multiplier using complementary voltage followerFull-text access may be available. Sign in or learn about subscription options.pp. 13,14,15,16,17,18
by S.C. Li, R. Chien, J. Chien, Kaung-Long Lin
HW-SW co-synthesis: the present and the futureFull-text access may be available. Sign in or learn about subscription options.pp. 19,20,21,22
by S. Parameswaran
Parallelization in co-compilation for configurable accelerators-a host/accelerator partitioning compilation methodFull-text access may be available. Sign in or learn about subscription options.pp. 23,24,25,26,27,28,29,30,31,32,33
by J. Becker, R. Hartenstein, M. Herz, U. Nageldinger
Delay and noise formulas for capacitively coupled distributed RC linesFull-text access may be available. Sign in or learn about subscription options.pp. 35,36,37,38,39,40,41,42,43
by H. Kawaguchi, T. Sakurai
Reduced order macromodel of coupled interconnects for timing and functional verification of sub-half-micron IC designsFull-text access may be available. Sign in or learn about subscription options.pp. 45,46,47,48,49,50
by D. Pandini, P. Scandelara, C. Guardiani
A new LSI performance prediction model for interconnection analysis of future LSIsFull-text access may be available. Sign in or learn about subscription options.pp. 51,52,53,54,55,56
by S. Takahashi, M. Edahiro, Y. Hayashi
New methods to find optimal non-disjoint bi-decompositionsFull-text access may be available. Sign in or learn about subscription options.pp. 59,60,61,62,63,64,65,66,67,68
by S. Yamashita, H. Sawada, A. Nagoya
A heuristic algorithm to design AND-OR-EXOR three-level networksFull-text access may be available. Sign in or learn about subscription options.pp. 69,70,71,72,73,74
by D. Debnath, T. Sasao
ETDD-based synthesis of term-based FPGAs for incompletely specified Boolean functionsFull-text access may be available. Sign in or learn about subscription options.pp. 75,76,77,78,79,80
by Gueesang Lee, R. Drechsler
Function decomposition and synthesis using linear siftingFull-text access may be available. Sign in or learn about subscription options.pp. 81,82,83,84,85,86
by C. Meinel, F. Somenzi, T. Theobald
Optimized array index computation in DSP programsFull-text access may be available. Sign in or learn about subscription options.pp. 87,88,89,90,91,92
by R. Leupers, A. Basu, P. Marwedel
Binding and scheduling algorithms for highly retargetable compilationFull-text access may be available. Sign in or learn about subscription options.pp. 93,94,95,96,97,98
by M. Yamaguchi, N. Ishiura, T. Kambe
Unrolling loops with indeterminate loop counts in system level pipelinesFull-text access may be available. Sign in or learn about subscription options.pp. 99,100,101,102,103,104
by Hui Guo, S. Paramewaran
Quantitative selection of media benchmarksFull-text access may be available. Sign in or learn about subscription options.pp. 105,106,107,108,109,110
by Chunho Lee, M. Potkonjak
Reliable threshold voltage determination for sub-0.1 /spl mu/m gate length MOSFETsFull-text access may be available. Sign in or learn about subscription options.pp. 111,112,113,114,115,116
by M. Tsuno, M. Suga, M. Tanaka, K. Shibahara, M. Miura-Mattausch, M. Hirose
Inverse modeling-a promising approach to know what is made and what should be madeFull-text access may be available. Sign in or learn about subscription options.pp. 117,118,119,120,121
by S. Yamaguchi, H. Goto
Concurrent technology, device, and circuit development for EEPROMsFull-text access may be available. Sign in or learn about subscription options.pp. 123,124,125,126,127,128
by U. Feldmann, R. Kakoschke, M. Miura-Mattausch, G. Schraud
TCAD/DA for MPU and ASIC developmentFull-text access may be available. Sign in or learn about subscription options.pp. 129,130,131,132,133,134
by H. Masuda, K. Tsuneno, H. Sato, K. Mori
Coupling Of Synthesis And Layout: Challenges And SolutionsFull-text access may be available. Sign in or learn about subscription options.pp. 135,136
by J. Cong
Logical-physical co-design for deep submicron circuits: challenges and solutionsFull-text access may be available. Sign in or learn about subscription options.pp. 137,138,139,140,141,142
by M. Pedram
Postion Paper For "Coupling Of Synthesis And Layout: Challenges And Solutions"Full-text access may be available. Sign in or learn about subscription options.pp. 143
by T. Mitsuhashi
A low power 2D DCT chip design using direct 2D algorithmFull-text access may be available. Sign in or learn about subscription options.pp. 145,146,147,148,149,150
by Liang-Gee Chen, Juing-Ying Jiu, Hao-Chieh Chang, Yung-Pin Lee, Chung-Wei Ku
Low power realization of FIR filters implemented using distributed arithmeticFull-text access may be available. Sign in or learn about subscription options.pp. 151,152,153,154,155,156
by M. Mehendale, A. Sinha, S.D. Sherlekar
An efficient variable-length tap FIR filter chipFull-text access may be available. Sign in or learn about subscription options.pp. 157,158,159,160,161
by Sung Hyun Yoon, M.H. Sunwoo
Effective simulation for the giga-scale massively parallel supercomputer SR2201Full-text access may be available. Sign in or learn about subscription options.pp. 163,164,165,166,167,168
by K. Suzuki, S. Miyamoto, M. Kurosaki, J. Nakagoshi
A top-down hardware/software co-simulation method for embedded systems based upon a component logical bus architectureFull-text access may be available. Sign in or learn about subscription options.pp. 169,170,171,172,173,174,175
by M. Yasuda, K. Seo, H. Koizumi, B. Shackleford, F. Suzuki
A hardware software cosimulation backplane with automatic interface generationFull-text access may be available. Sign in or learn about subscription options.pp. 177,178,179,180,181,182
by Wonyong Sung, Soonhoi Ha
On the CSC property of signal transition graph specifications for asynchronous circuit designFull-text access may be available. Sign in or learn about subscription options.pp. 183,184,185,186,187,188,189
by M. Sahni, T. Nanya
Practical synthesis of speed-independent circuits using unfoldingsFull-text access may be available. Sign in or learn about subscription options.pp. 191,192,193,194,195,196
by Uisok Kim, Dong-Ik Lee
Automated design of wave pipelined multiport register filesFull-text access may be available. Sign in or learn about subscription options.pp. 197,198,199,200,201,202
by K. Takano, T. Sasaki, N. Oba, H. Kobayashi, T. Nakamura
Design And EDA RoadmapFull-text access may be available. Sign in or learn about subscription options.pp. 203
by G. Ledenbach
Considering testability during high-level designFull-text access may be available. Sign in or learn about subscription options.pp. 205,206,207,208,209,210
by S. Dey, A. Raghunathan, R.K. Roy
Partial scan design methods based on internally balanced structureFull-text access may be available. Sign in or learn about subscription options.pp. 211,212,213,214,215,216
by T. Takasaki, T. Inoue, H. Fujiwara
Model checking: its basics and realityFull-text access may be available. Sign in or learn about subscription options.pp. 217,218,219,220,221,222
by M. Fujita
A survey for pass-transistor logic technologies-recent researches and developments and future prospectsFull-text access may be available. Sign in or learn about subscription options.pp. 223,224,225,226
by K. Taki
ALPS: an automatic layouter for pass-transistor cell synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 227,228,229,230,231,232
by Y. Sasaki, K. Rikino, K. Yano
NTRS-97 - Upcoming Deep Sub Micron Eda Tools RequirementsFull-text access may be available. Sign in or learn about subscription options.pp. 233
by G. Ledenbach
Software licensing models in the EDA industryFull-text access may be available. Sign in or learn about subscription options.pp. 235,236,237,238,239
by D.R. Bettadapur
Pre-layout delay calculation specification for CMOS ASIC librariesFull-text access may be available. Sign in or learn about subscription options.pp. 241,242,243,244,245,246,247,248
by H. Edamatsu, K. Homma, M. Kakimoto, Y. Koike, K. Tabuchi
CHDStd-a model for deep submicron design toolsFull-text access may be available. Sign in or learn about subscription options.pp. 249,250,251,252,253,254,255
by D. Cottrell, D. Mallis, J. Morrell
Hierarchy-a CHDStd tool for the coming deep submicron complex design crisisFull-text access may be available. Sign in or learn about subscription options.pp. 257,258,259,260
by S. Grout, G. Ledenbach, R.G. Bushroe, P. Fisher, D. Cottrell, D. Mallis, S. DasGupta, J. Morrell, J. Sayah, R. Gupta, P.T. Patel, P. Adams
ATM cell modelling using objective VHDLFull-text access may be available. Sign in or learn about subscription options.pp. 261,262,263,264
by A. Allara, M. Bombana, P. Cavalloro, W. Nebel, W. Putzke, M. Radetzki
A high-level synthesis system for digital signal processing based on enumerating data-flow graphsFull-text access may be available. Sign in or learn about subscription options.pp. 265,266,267,268,269,270,271,272,273,274
by N. Togawa, T. Hisaki, M. Yanagisawa, T. Ohtsuki
Module selection using manufacturing informationFull-text access may be available. Sign in or learn about subscription options.pp. 275,276,277,278,279,280,281
by H. Tomiyama, H. Yasuura
Techniques for functional test pattern executionFull-text access may be available. Sign in or learn about subscription options.pp. 283,284,285,286,287,288
by I. Hong, M. Potkonjak
Heterogeneous BISR-approach using system level synthesis flexibilityFull-text access may be available. Sign in or learn about subscription options.pp. 289,290,291,292,293,294
by I. Hong, M. Potkonjak, R. Karri
An integrated flow for technology remapping and placement of sub-half-micron circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 295,296,297,298,299,300
by J. Lou, A.H. Salek, M. Pedram
Scan-chain optimization algorithms for multiple scan-pathsFull-text access may be available. Sign in or learn about subscription options.pp. 301,302,303,304,305,306
by S. Kobayashi, M. Edahiro, M. Kubo
A clock-gating method for low-power LSI designFull-text access may be available. Sign in or learn about subscription options.pp. 307,308,309,310,311,312
by T. Kitahara, F. Minami, T. Ueda, K. Usami, S. Nishio, M. Murakata, T. Mitsuhashi
Power reduction in microprocessor chips by gated clock routingFull-text access may be available. Sign in or learn about subscription options.pp. 313,314,315,316,317,318
by Jaewon Oh, M. Pedram
TITAC-2: an asynchronous 32-bit microprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 319,320
by A. Takamura, M. Imai, M. Ozawa, I. Fukasaku, T. Fujii, M. Kuwako, Y. Ueno, T. Nanya
Power-Pro: programmable power management architectureFull-text access may be available. Sign in or learn about subscription options.pp. 321,322
by T. Ishihara, H. Yasuura
Low power microprocessors for comparative study on bus architecture and multiplexer architectureFull-text access may be available. Sign in or learn about subscription options.pp. 323,324
by S. Komatsu, M. Ikeda, K. Asada
MetaCore: a configurable & instruction-level extensible DSP coreFull-text access may be available. Sign in or learn about subscription options.pp. 325,326
by Jin-Hyuk Yang, Byoung-Woon Kim, Sung-Won Seo, Sang-Jun Nam, Chang-Ho Ryu, Jang-Ho Cho, Chong-Min Kyung
A design of sound synthesis ICFull-text access may be available. Sign in or learn about subscription options.pp. 327,328
by Ho Keun Jang
An efficient 2-D convolver chip for real-time image processingFull-text access may be available. Sign in or learn about subscription options.pp. 329,330
by Se Young Eun, M.H. Sunwoo
FPGA for high-performance bit-serial pipeline datapathFull-text access may be available. Sign in or learn about subscription options.pp. 331,332
by T. Isshiki, T. Shimizugashira, A. Ohta, I. Amril, H. Kunieda
A new multiport memory for high performance parallel processor system with shared memoryFull-text access may be available. Sign in or learn about subscription options.pp. 333,334
by K. Hirano, T. Ono, H. Kurino, M. Koyanagi
A low power 50 MHz FFT processor with cyclic extension and shaping filterFull-text access may be available. Sign in or learn about subscription options.pp. 335,336
by M. Bickerstaff, T. Arivoli, P.J. Ryan, N. Weste, D. Skellern
The MINC (Multistage Interconnection Network with Cache control mechanism) chipFull-text access may be available. Sign in or learn about subscription options.pp. 337,338
by T. Midorikawa, T. Kamei, T. Hanawa, H. Amano
A CMOS smart image sensor LSI for focal-plane compressionFull-text access may be available. Sign in or learn about subscription options.pp. 339,340
by S. Kawahito, M. Yoshida, M. Sasaki, D. Miyazaki, Y. Tadokoro, K. Murata, S. Doushou, A. Matsuzawa
A /spl plusmn/1.5 V, 4 MHz low-pass Gm-C filter in CMOSFull-text access may be available. Sign in or learn about subscription options.pp. 341,342
by Changsik Yoo, Wonchan Kim
Motion adaptive image sensorFull-text access may be available. Sign in or learn about subscription options.pp. 343,344
by T. Hamamoto, K. Aizawa, M. Hatori
Timing Analysis And Optimization: From Devices To SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 345
by A. Devgan, S. Kundu
Dual-loop digital PLL design for adaptive clock recoveryFull-text access may be available. Sign in or learn about subscription options.pp. 347,348,349,350,351,352
by Tae Hun Kim, Beomsup Kim
High-level estimation techniques for usage in hardware/software co-designFull-text access may be available. Sign in or learn about subscription options.pp. 353,354,355,356,357,358,359,360
by J. Henkel, R. Ernst
Loop pipelining in hardware-software partitioningFull-text access may be available. Sign in or learn about subscription options.pp. 361,362,363,364,365,366
by Jinhwan Jeon, Kiyoung Choi
A performance maximization algorithm to design ASIPs under the constraint of chip area including RAM and ROM sizesFull-text access may be available. Sign in or learn about subscription options.pp. 367,368,369,370,371,372
by Nguyen Ngoc Binh, M. Imai, Y. Takeuchi
Simultaneous wire sizing and wire spacing in post-layout performance optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 373,374,375,376,377,378
by Jiang-An He, H. Kobayashi
Hierarchical LVS based on hierarchy rebuildingFull-text access may be available. Sign in or learn about subscription options.pp. 379,380,381,382,383,384
by Wonjong Kim, Hyunchul Shin
Curvilinear detailed routing algorithm and its extension to wire-spreading and wire-fatteningFull-text access may be available. Sign in or learn about subscription options.pp. 385,386,387,388,389,390
by T. Hama, H. Etoh
Tool capabilities needed for designing 100 MHz interconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 391,392,393,394,395
by T.A. Schreyer
Development of a support tool for PCB design with EMC constraint. Reflection and crosstalk noise reduction in manual designFull-text access may be available. Sign in or learn about subscription options.pp. 397,398,399,400,401,402
by Y. Tarui, T. Takahashi, N. Schibuya
An analysis on VLSI interconnection considering skin effectFull-text access may be available. Sign in or learn about subscription options.pp. 403,404,405,406,407,408
by T. Mido, K. Asada
Design of nonlinear switched-current circuits using building block approachFull-text access may be available. Sign in or learn about subscription options.pp. 409,410,411,412,413,414
by X. Zeng, P.S. Tang, C.K. Tse
A new design of double edge triggered flip-flopsFull-text access may be available. Sign in or learn about subscription options.pp. 417,418,419,420,421
by M. Pedram, Qing Wu, Xunwei Wu
Space- and time-efficient BDD construction via working set controlFull-text access may be available. Sign in or learn about subscription options.pp. 423,424,425,426,427,428,429,430,431,432
by Bwolen Yang, Yirng-An Chen, R.E. Bryant, D.R. O'Hallaron
Manipulation of *BMDsFull-text access may be available. Sign in or learn about subscription options.pp. 433,434,435,436,437,438
by R. Drechsler, S. Horeth
Decision diagrams for discrete functions: classification and unified interpretationFull-text access may be available. Sign in or learn about subscription options.pp. 439,440,441,442,443,444,445,446
by R.S. Stankovic, T. Sasao
Reconfigurable systems: a surveyFull-text access may be available. Sign in or learn about subscription options.pp. 447,448,449,450,451,452
by T. Miyazaki
Reconfigurable systems: activities in Asia and South PacificFull-text access may be available. Sign in or learn about subscription options.pp. 453,454,455,456,457
by H. Amano, Y. Shibata
Asian-Pacific LSI business in the 21st centuryFull-text access may be available. Sign in or learn about subscription options.pp. 459
by O. Karatsu
LSI business of China in 21st centuryFull-text access may be available. Sign in or learn about subscription options.pp. 461,462
by Z.Y. Xu
A redundant fault identification algorithm with Exclusive-OR circuit reductionFull-text access may be available. Sign in or learn about subscription options.pp. 463,464,465,466,467,468
by M. Tandai, T. Shinsha
Interchangeable boolean functions and their effects on redundancy in logic circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 469,470,471,472,473,474
by D.K. Das, S. Chakraborty, B.B. Bhattacharya
Real time fault injection using logic emulatorsFull-text access may be available. Sign in or learn about subscription options.pp. 475,476,477,478,479
by R. Sedaghat-Maman, E. Barke
Integer programming models for optimization problems in test generationFull-text access may be available. Sign in or learn about subscription options.pp. 481,482,483,484,485,486,487
by J.P. Marques Silva
A fast and accurate method of redesigning analog subcircuits for technology scalingFull-text access may be available. Sign in or learn about subscription options.pp. 489,490,491,492,493,494
by S. Funaba, A. Kitagawa, T. Tsukada, G. Yokomizo
A novel design assistant for analog circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 495,496,497,498,499,500
by M. Wolf, U. Kleine, F. Schafer
Automatic test generation of linear analog circuits under parameter variationsFull-text access may be available. Sign in or learn about subscription options.pp. 501,502,503,504,505,506
by C.-J. R. Shi, M.W. Tian
The ensparsed LU decomposition method for large scale circuit transient analysisFull-text access may be available. Sign in or learn about subscription options.pp. 507,508,509,510,511,512
by R. Suda, Y. Oyanagi
FPART: a multi-way FPGA partitioning procedure based on the improved FM algorithmFull-text access may be available. Sign in or learn about subscription options.pp. 513,514,515,516,517,518
by Z. Rongzheng, T. Jiarong, T. Pushan
An incremental placement and global routing algorithm for field-programmable gate arraysFull-text access may be available. Sign in or learn about subscription options.pp. 519,520,521,522,523,524,525,526
by N. Togawa, K. Hagi, M. Yanagisawa, T. Ohtsuki
An architecture-oriented routing method for FPGAs having rich hierarchical routing resourcesFull-text access may be available. Sign in or learn about subscription options.pp. 527,528,529,530,531,532,533
by T. Murooka, A. Takahara, T. Miyazaki, A. Tsutsui
On the optimal sub-routing structures of 2-D FPGA greedy routing architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 535,536,537,538,539,540
by Jiaofeng Pan, Yu-Liang Wu, C.K. Wong
Mixed-signal Hardware Description Languages In The Era Of System-on-silicon: Challenges And OpportunitiesFull-text access may be available. Sign in or learn about subscription options.pp. 543
by C.-J.R. Shi
Power reduction in pipelinesFull-text access may be available. Sign in or learn about subscription options.pp. 545,546,547,548,549,550
by S. Parameswaran, Hui Guo
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