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Proceedings of the Fourth Asian Test Symposium

Nov. 23 1995 to Nov. 24 1995

Bangalore, India

ISBN: 0-8186-7129-7

Table of Contents

General Chair's MessageFreely available from IEEE.pp. xi
Program Chair's MessageFreely available from IEEE.pp. xii
Organizing Committee and SponsorsFreely available from IEEE.pp. xv
Program CommitteeFreely available from IEEE.pp. xvii
ReviewersFreely available from IEEE.pp. xviii
Session 1 - Systems Test, Chair: D. Nikolos, University of Patras, Greece
Distributed off-line testing of parallel systemsFull-text access may be available. Sign in or learn about subscription options.pp. 2
Session 1 - Systems Test, Chair: D. Nikolos, University of Patras, Greece
An SBus Multi-Tracer and its applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 9
Session 1 - Systems Test, Chair: D. Nikolos, University of Patras, Greece
Exploitation of parallelism in group probing for testing massively parallel processing systemsFull-text access may be available. Sign in or learn about subscription options.pp. 15
Session 1 - Systems Test, Chair: D. Nikolos, University of Patras, Greece
A cellular array designed from a Multiple-valued Decision Diagram and its fault testsFull-text access may be available. Sign in or learn about subscription options.pp. 20
Session 2 - Analysis Techniques, Chair: S. Xu, Shanghai University of Science and Technology, China
Boolean process-an analytical approach to circuit representation (II)Full-text access may be available. Sign in or learn about subscription options.pp. 26
Session 2 - Analysis Techniques, Chair: S. Xu, Shanghai University of Science and Technology, China
Fanout fault analysis for digital logic circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 33-39
Session 2 - Analysis Techniques, Chair: S. Xu, Shanghai University of Science and Technology, China
Metastability evaluation method by propagation delay distribution measurementFull-text access may be available. Sign in or learn about subscription options.pp. 40
Session 2 - Analysis Techniques, Chair: S. Xu, Shanghai University of Science and Technology, China
An approach to hierarchy model checking via evaluating CTL hierarchicallyFull-text access may be available. Sign in or learn about subscription options.pp. 45
Session 3 - Diagnosis, Chair: B. Courtois, TZMA, France
Transistor leakage fault location with ZDDQ measurementFull-text access may be available. Sign in or learn about subscription options.pp. 51
Session 3 - Diagnosis, Chair: B. Courtois, TZMA, France
Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testingFull-text access may be available. Sign in or learn about subscription options.pp. 58
Session 3 - Diagnosis, Chair: B. Courtois, TZMA, France
A simple technique for locating gate-level faults in combinational circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 65
Session 3 - Diagnosis, Chair: B. Courtois, TZMA, France
A fault location technique and alternate routing in Benes networkFull-text access may be available. Sign in or learn about subscription options.pp. 71
Session 4 - Fault Simulation, Chair: C.L. Lee, National Chiao Tung University, Taiwan
Overhead reduction techniques for hierarchical fault simulationFull-text access may be available. Sign in or learn about subscription options.pp. 79
Session 4 - Fault Simulation, Chair: C.L. Lee, National Chiao Tung University, Taiwan
On the simulation of Multiple Stuck-at Faults using Multiple Domain Concurrent and Comparative SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 86
Session 4 - Fault Simulation, Chair: C.L. Lee, National Chiao Tung University, Taiwan
Fast fault simulation for BIST applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 93
Session 4 - Fault Simulation, Chair: C.L. Lee, National Chiao Tung University, Taiwan
Serial transistor network modeling for bridging fault simulationFull-text access may be available. Sign in or learn about subscription options.pp. 100
Session 4 - Fault Simulation, Chair: C.L. Lee, National Chiao Tung University, Taiwan
Hardware-accelerated concurrent fault simulation: eventflow computing versus dataflow computingFull-text access may be available. Sign in or learn about subscription options.pp. 107
Session 5 - Mixed-Signal Test, Chair: M.M. Hasan, UT Kanpur, India
A design-for-test technique for multistage analog circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 113
Session 5 - Mixed-Signal Test, Chair: M.M. Hasan, UT Kanpur, India
DC control and observation structures for analog circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 120
Session 5 - Mixed-Signal Test, Chair: M.M. Hasan, UT Kanpur, India
A new method for testing mixed analog and digital circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 127
Session 5 - Mixed-Signal Test, Chair: M.M. Hasan, UT Kanpur, India
On the development of power supply voltage control testing technique for analogue circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 133
Session 5 - Mixed-Signal Test, Chair: M.M. Hasan, UT Kanpur, India
Tolerance DC bands of CMOS operational amplifierFull-text access may be available. Sign in or learn about subscription options.pp. 140
Session 6 - Design for Testability, Chair: C-S. Lin, National Taiwan University, Taiwan
Theory and applications of cellular automata for synthesis of easily testable combinational logicFull-text access may be available. Sign in or learn about subscription options.pp. 146
Session 6 - Design for Testability, Chair: C-S. Lin, National Taiwan University, Taiwan
Unified scan design with scannable memory arraysFull-text access may be available. Sign in or learn about subscription options.pp. 153
Session 6 - Design for Testability, Chair: C-S. Lin, National Taiwan University, Taiwan
Test configurations to enhance the testability of sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 160
Session 6 - Design for Testability, Chair: C-S. Lin, National Taiwan University, Taiwan
Test sequence compaction by reduced scan shift and retimingFull-text access may be available. Sign in or learn about subscription options.pp. 169
Session 6 - Design for Testability, Chair: C-S. Lin, National Taiwan University, Taiwan
Testable design of non-scan sequential circuits using extra logicFull-text access may be available. Sign in or learn about subscription options.pp. 176
Session 7 - Education and Research in Testing, Chair: V.D. Agrawal, AT&T Bell Labs, USA
Training diploma students on ATE-related moduleFull-text access may be available. Sign in or learn about subscription options.pp. 184
Panel
New Research Problems in the Emerging Test TechnologyFull-text access may be available. Sign in or learn about subscription options.pp. 189
Session 8 - Testability Measures, Chair: B.B. Bhattacharya, ISI, India
A STAFAN-like functional testability measure for register-level circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 192
Session 8 - Testability Measures, Chair: B.B. Bhattacharya, ISI, India
Testability forecasting for sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 199
Session 8 - Testability Measures, Chair: B.B. Bhattacharya, ISI, India
Testability analysis of co-designed systemsFull-text access may be available. Sign in or learn about subscription options.pp. 206
Session 9 - Delay Test I, Chair: P. Varma, CrossCheck, USA
Generator choices for delay testFull-text access may be available. Sign in or learn about subscription options.pp. 214
Session 9 - Delay Test I, Chair: P. Varma, CrossCheck, USA
Static compaction for two-pattern test setsFull-text access may be available. Sign in or learn about subscription options.pp. 222
Session 9 - Delay Test I, Chair: P. Varma, CrossCheck, USA
Identification of robust untestable path delay faultsFull-text access may be available. Sign in or learn about subscription options.pp. 229
Session 10 - ATPG, Chair: S. Kundu, IBM, USA
An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 237
Session 10 - ATPG, Chair: S. Kundu, IBM, USA
Deterministic test generation for non-classical faults on the gate levelFull-text access may be available. Sign in or learn about subscription options.pp. 244
Session 10 - ATPG, Chair: S. Kundu, IBM, USA
A parallel sequential test generation system DESCARTES based on real-valued logic simulationFull-text access may be available. Sign in or learn about subscription options.pp. 252
Session 10 - ATPG, Chair: S. Kundu, IBM, USA
Universal test complexity of field-programmable gate arraysFull-text access may be available. Sign in or learn about subscription options.pp. 259
Session 10 - ATPG, Chair: S. Kundu, IBM, USA
Software transformations for sequential test generationFull-text access may be available. Sign in or learn about subscription options.pp. 266
Session 11 - BIST, Chair: K. Furuya, Chuo University, Japan
Module level weighted random patternsFull-text access may be available. Sign in or learn about subscription options.pp. 274
Session 11 - BIST, Chair: K. Furuya, Chuo University, Japan
A programmable multiple-sequence generator for BIST applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 279
Session 11 - BIST, Chair: K. Furuya, Chuo University, Japan
An effective BIST design for PLAFull-text access may be available. Sign in or learn about subscription options.pp. 286
Session 11 - BIST, Chair: K. Furuya, Chuo University, Japan
Fast computation of C-MISR signaturesFull-text access may be available. Sign in or learn about subscription options.pp. 293
Session 11 - BIST, Chair: K. Furuya, Chuo University, Japan
An effective BIST scheme for carry-save and carry-propagate array multipliersFull-text access may be available. Sign in or learn about subscription options.pp. 298
Session 11 - BIST, Chair: K. Furuya, Chuo University, Japan
Error masking in compact testing based on the Hamming code and its modificationsFull-text access may be available. Sign in or learn about subscription options.pp. 303
Session 12 - Self-Checking Circuits, Chair: B. Mitra, Texas Instruments, India
An efficient comparative concurrent Built-In Self-Test techniqueFull-text access may be available. Sign in or learn about subscription options.pp. 309
Session 12 - Self-Checking Circuits, Chair: B. Mitra, Texas Instruments, India
Totally Self Checking reconfigurable duplication system with separate internal fault indicationFull-text access may be available. Sign in or learn about subscription options.pp. 316
Session 12 - Self-Checking Circuits, Chair: B. Mitra, Texas Instruments, India
Generalized modular design of testable m-out-of-n code checkerFull-text access may be available. Sign in or learn about subscription options.pp. 322
Session 12 - Self-Checking Circuits, Chair: B. Mitra, Texas Instruments, India
A graph coloring based approach for self-checking logic circuit designFull-text access may be available. Sign in or learn about subscription options.pp. 327
Session 13 - Delay Test II, Chair: Y. Min, ICT, China
Generation of tenacious tests for small gate delay faults in combinational circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 332
Session 13 - Delay Test II, Chair: Y. Min, ICT, China
Functional test generation for path delay faultsFull-text access may be available. Sign in or learn about subscription options.pp. 339
Session 13 - Delay Test II, Chair: Y. Min, ICT, China
Flip-flop sharing in standard scan path to enhance delay fault testing of sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 346
Session 13 - Delay Test II, Chair: Y. Min, ICT, China
Sequential logic path delay test generation by symbolic analysisFull-text access may be available. Sign in or learn about subscription options.pp. 353
Session 14 - Technology-Specific Test, Chair: M. Franklin, Clemson University, USA
Low power design and its testabilityFull-text access may be available. Sign in or learn about subscription options.pp. 361
Session 14 - Technology-Specific Test, Chair: M. Franklin, Clemson University, USA
Power supply current detectability of SRAM defectsFull-text access may be available. Sign in or learn about subscription options.pp. 367
Session 15 - Design-Specific Test, Chair: H. Fujiwara, NAIST, Japan
Fast functional testing of delay-insensitive circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 375
Session 15 - Design-Specific Test, Chair: H. Fujiwara, NAIST, Japan
DFT for fast testing of self-timed control circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 382
Session 15 - Design-Specific Test, Chair: H. Fujiwara, NAIST, Japan
Testing of a parallel ternary multiplier using I/sup 2/L logicFull-text access may be available. Sign in or learn about subscription options.pp. 387
Session 15 - Design-Specific Test, Chair: H. Fujiwara, NAIST, Japan
Author IndexFreely available from IEEE.pp. 393
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