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2003 Test Symposium

Nov. 16 2003 to Nov. 19 2003

Xi?an, China

ISSN: 1081-7735

ISBN: 0-7695-1951-2

Table of Contents

Proceedings of the Twelfth Asian Symposium, ATS 2003Full-text access may be available. Sign in or learn about subscription options.
Improving test quality of scan-based BIST by scan chain partitioningFull-text access may be available. Sign in or learn about subscription options.pp. 12-17
Introduction
Message from the Symposium ChairsFreely available from IEEE.pp. xv
Introduction
Message from the Program ChairsFreely available from IEEE.pp. xvi
Introduction
ATS Steering CommitteeFreely available from IEEE.pp. xvii
Introduction
The 12th Asian Test Symposium CommitteeFreely available from IEEE.pp. xviii
Introduction
Program CommitteeFreely available from IEEE.pp. xix
Introduction
ReviewersFreely available from IEEE.pp. xxi
Introduction
TTTC Activities BoardFreely available from IEEE.pp. 515
Plenary Session: Keynote Address
Outstanding Challenges in Testing Nanotechnology Based Integrated CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 2
Plenary Session: Keynote Address
Leveraging Infrastructure IP for SoC YieldFull-text access may be available. Sign in or learn about subscription options.pp. 3
Session 1A: Design for Testability
Reducing Scan Shifts Using Folding Scan TreesFull-text access may be available. Sign in or learn about subscription options.pp. 6
Session 1A: Design for Testability
Improving Test Quality of Scan-Based BIST by Scan Chain PartitioningFull-text access may be available. Sign in or learn about subscription options.pp. 12
Session 1A: Design for Testability
IC Reliability Simulator ARET and Its Application in Design-for-ReliabilityFull-text access may be available. Sign in or learn about subscription options.pp. 18
Session 1B: Memory Testing 1
Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance TracesFull-text access may be available. Sign in or learn about subscription options.pp. 24
Session 1B: Memory Testing 1
Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL ToolFull-text access may be available. Sign in or learn about subscription options.pp. 32
Session 1C: Fault Diagnosis 1
Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 38
Session 1C: Fault Diagnosis 1
Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 44
Session 1C: Fault Diagnosis 1
A Linear Time Fault Diagnosis Algorithm for Hypercube Multiprocessors under the MM* Comparison ModelFull-text access may be available. Sign in or learn about subscription options.pp. 50
Session 2A: Delay Testing
Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault ModelsFull-text access may be available. Sign in or learn about subscription options.pp. 58
Session 2A: Delay Testing
On Estimation of Fault Efficiency for Path Delay FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 64
Session 2A: Delay Testing
Software-Based Delay Fault Testing of Processor CoresFull-text access may be available. Sign in or learn about subscription options.pp. 68
A DFT approach for path delay faults in interconnected circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 72-75
Session 2B: BIST
A BIST Architecture for FPGA Look-Up Table Testing Reduces ReconfigurationsFull-text access may be available. Sign in or learn about subscription options.pp. 84
Session 2B: BIST
A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor LogicFull-text access may be available. Sign in or learn about subscription options.pp. 90
Session 2C: Software Testing 1
Domain Testing Based on Character String PredicateFull-text access may be available. Sign in or learn about subscription options.pp. 96
Session 2C: Software Testing 1
Automated TTCN-3 Test Case Generation by Means of UML Sequence Diagrams and Markov ChainsFull-text access may be available. Sign in or learn about subscription options.pp. 102
Session 2C: Software Testing 1
Efficiency Analysis and Safety Assessment of Automatic Testing for Safety-Critical SoftwareFull-text access may be available. Sign in or learn about subscription options.pp. 106
Session 2C: Software Testing 1
An Expression?s Single Fault Model and the Testing MethodsFull-text access may be available. Sign in or learn about subscription options.pp. 110
Session 3A: Mixed-Signal Testing
PLL Based High Speed Functional TestingFull-text access may be available. Sign in or learn about subscription options.pp. 116
Session 3A: Mixed-Signal Testing
Issues Related to the Formulation of DFT Solution for Analog Circuit Test Using Equivalent Fault AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 120
Session 3A: Mixed-Signal Testing
A Sigma-Delta Modulation Based BIST Scheme for A/D ConvertersFull-text access may be available. Sign in or learn about subscription options.pp. 124
Session 3B: Test Compaction 1
A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area ConstraintFull-text access may be available. Sign in or learn about subscription options.pp. 130
Session 3B: Test Compaction 1
Optimal Scan Tree Construction with Test Vector Modification for Test CompressionFull-text access may be available. Sign in or learn about subscription options.pp. 136
Session 3B: Test Compaction 1
STAGE: A Decoding Engine Suitable for Multi-Compressed Test DataFull-text access may be available. Sign in or learn about subscription options.pp. 142
Session 3C: RTL Verification
Automatic Design Validation Framework for HDL Descriptions via RTL ATPGFull-text access may be available. Sign in or learn about subscription options.pp. 148
Session 3C: RTL Verification
An Automatic Circuit Extractor for RTL VerificationFull-text access may be available. Sign in or learn about subscription options.pp. 154
Session 3C: RTL Verification
An Efficient Observability Evaluation Algorithm Based on Factored Use-Def ChainsFull-text access may be available. Sign in or learn about subscription options.pp. 161
Session 4A: Enhanced Delay Testing and ATPG
Delay Testing of MOS Transistor with Gate Oxide ShortFull-text access may be available. Sign in or learn about subscription options.pp. 168
Session 4A: Enhanced Delay Testing and ATPG
An Enhanced Test Generator for Capacitance Induced Crosstalk Delay FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 174
Session 4A: Enhanced Delay Testing and ATPG
Delay Test Pattern Generation Considering Crosstalk-Induced EffectsFull-text access may be available. Sign in or learn about subscription options.pp. 178
Session 4A: Enhanced Delay Testing and ATPG
Automated Test Model Generation from Switch Level Custom CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 184
Session 4B: Test Power
Power Conscious BIST Design for Sequential Circuits Using ghost-FSMFull-text access may be available. Sign in or learn about subscription options.pp. 190
Session 4B: Test Power
Average Leakage Current Macromodeling for Dual-Threshold Voltage CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 196
Session 4B: Test Power
Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan TestFull-text access may be available. Sign in or learn about subscription options.pp. 202
Session 4C: Software Testing 2
Analysis of Software Test Item Generation — Comparison between High Skilled and Low Skilled EngineersFull-text access may be available. Sign in or learn about subscription options.pp. 210
Session 4C: Software Testing 2
Conformance Test of Distributed Transaction ServiceFull-text access may be available. Sign in or learn about subscription options.pp. 216
Session 4C: Software Testing 2
Build-In-Self-Test for SoftwareFull-text access may be available. Sign in or learn about subscription options.pp. 220
Session 4C: Software Testing 2
Testing the Conformity of Transactional Attributes of Components by SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 224
Session 5A: Fault Diagnosis 2
Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault InformationFull-text access may be available. Sign in or learn about subscription options.pp. 230
Session 5A: Fault Diagnosis 2
Fault Diagnosis for Physical Defects of Unknown BehaviorsFull-text access may be available. Sign in or learn about subscription options.pp. 236
Session 5A: Fault Diagnosis 2
Fault Detection for Testable Realizations of Multiple-Valued Logic FunctionsFull-text access may be available. Sign in or learn about subscription options.pp. 242
Session 5B: Memory Testing 2
Comparison of Open and Resistive-Open Defect Test Conditions in SRAM Address DecodersFull-text access may be available. Sign in or learn about subscription options.pp. 250
Session 5B: Memory Testing 2
Defect Oriented Fault Analysis for SRAMFull-text access may be available. Sign in or learn about subscription options.pp. 256
Session 5B: Memory Testing 2
A Novel Method for Online In-Place Detection and Location of Multiple Interconnect Faults in SRAM Based FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 262
Session 5C: SOC Test
Between-Core Vector Overlapping for Test Cost Reduction in Core TestingFull-text access may be available. Sign in or learn about subscription options.pp. 268
Session 5C: SOC Test
The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation MethodologyFull-text access may be available. Sign in or learn about subscription options.pp. 274
Session 5C: SOC Test
A Test Generation Approach for Systems-on-Chip that Use Intellectual Property CoresFull-text access may be available. Sign in or learn about subscription options.pp. 278
Session 6A: DFT Synthesis
Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault TestabilityFull-text access may be available. Sign in or learn about subscription options.pp. 284
Session 6A: DFT Synthesis
BDD Based Synthesis of Symmetric Functions with Full Path-Delay Fault TestabilityFull-text access may be available. Sign in or learn about subscription options.pp. 290
Session 6A: DFT Synthesis
Test Synthesis for Datapaths Using Datapath-Controller FunctionsFull-text access may be available. Sign in or learn about subscription options.pp. 294
Session 6A: DFT Synthesis
Non-Scan Design for Testability for Mixed RTL Circuits with Both Data Paths and Controller via Conflict AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 300
Session 6B: Test Scheduling
Optimal System-on-Chip Test SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 306
Session 6B: Test Scheduling
SOC Test Time Minimization Under Multiple ConstraintsFull-text access may be available. Sign in or learn about subscription options.pp. 312
Session 6B: Test Scheduling
Test Time Minimization for Hybrid BIST of Core-Based SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 318
Session 6C: Measurement
On-Chip Short-Time Interval Measurement for High-Speed Signal Timing CharacterizationFull-text access may be available. Sign in or learn about subscription options.pp. 326
Author indexFreely available from IEEE.pp. 511-513
Session 6C: Measurement
An On-Chip Jitter Measurement Circuit for the PLLFull-text access may be available. Sign in or learn about subscription options.pp. 332
Session 6C: Measurement
A Low-Cost Jitter Measurement Technique for BIST ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 336
Session 6C: Measurement
Measurement-Based Modeling with Adaptive SamplingFull-text access may be available. Sign in or learn about subscription options.pp. 340
Session 7A: Test Economics
Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device TestingFull-text access may be available. Sign in or learn about subscription options.pp. 348
Session 7A: Test Economics
Minimizing Defective Part Level Using a Linear Programming-Based Optimal Test Selection MethodFull-text access may be available. Sign in or learn about subscription options.pp. 354
Session 7A: Test Economics
Lowering Cost of Test: Parallel Test or Low-Cost ATE?Full-text access may be available. Sign in or learn about subscription options.pp. 360
Session 7B: Memory Testing 3
A Processor-Based Built-In Self-Repair Design for Embedded MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 366
Session 7B: Memory Testing 3
March SL: A Test For All Static Linked Memory FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 372
Session 7B: Memory Testing 3
Testing Delay Faults in Embedded CAMsFull-text access may be available. Sign in or learn about subscription options.pp. 378
Session 7B: Memory Testing 3
Stress Test for Disturb Faults in Non-Volatile MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 384
Session 7C: Current Test
A BIST Circuit for IDDQ TestsFull-text access may be available. Sign in or learn about subscription options.pp. 390
Session 7C: Current Test
At-Speed Current TestingFull-text access may be available. Sign in or learn about subscription options.pp. 396
Session 7C: Current Test
IDDT ATPG Based on Ambiguous Delay AssignmentsFull-text access may be available. Sign in or learn about subscription options.pp. 400
Session 7C: Current Test
Improvement of Detectability for CMOS Floating Gate Defects in Supply Current TestFull-text access may be available. Sign in or learn about subscription options.pp. 406
Session 8A: SOC DFT
A DFT Selection Method for Reducing Test Application Time of System-on-ChipsFull-text access may be available. Sign in or learn about subscription options.pp. 412
Session 8A: SOC DFT
Sharing BIST with Multiple Cores for System-on-a-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 418
Session 8A: SOC DFT
Designing Multiple Scan Chains for Systems-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 424
Session 8A: SOC DFT
Optimizing Test Access Mechanism under Constraints by Genetic Local Search AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 428
Test data volume reduction by test data realignmentFull-text access may be available. Sign in or learn about subscription options.pp. 434-439
Session 8B: Test Compaction 2
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels ReductionFull-text access may be available. Sign in or learn about subscription options.pp. 440
Session 8B: Test Compaction 2
Test Response Compression Based on Huffman CodingFull-text access may be available. Sign in or learn about subscription options.pp. 446
Session 8C: Functional Testing/Reliability
Probability Model for Faults in Large-Scale Multicomputer SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 452
Session 8C: Functional Testing/Reliability
Design Retargetable Platform System for Microprocessor Functional TestFull-text access may be available. Sign in or learn about subscription options.pp. 458
Session 8C: Functional Testing/Reliability
Assessing Software Implemented Fault Detection and Fault Tolerance MechanismsFull-text access may be available. Sign in or learn about subscription options.pp. 462
Session 8C: Functional Testing/Reliability
Briefing a New Approach to Improve the EMI Immunity of DSP SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 468
Session 9A: Formal Verification
Design Error Diagnosis Based on Verification TechniquesFull-text access may be available. Sign in or learn about subscription options.pp. 474
Session 9A: Formal Verification
SAT-Based Algorithm of Verification for Port Order FaultFull-text access may be available. Sign in or learn about subscription options.pp. 478
Session 9A: Formal Verification
Equivalence Checking Using Independent CutsFull-text access may be available. Sign in or learn about subscription options.pp. 482
Session 9B: Software Testing 3
A Method to Calculate the Reliability of Component-Based SoftwareFull-text access may be available. Sign in or learn about subscription options.pp. 488
Session 9B: Software Testing 3
An Object-Oriented Program Automatic Execute Model and the Research of AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 492
Session 9B: Software Testing 3
User-Level Implementation of Checkpointing for Multithreaded Applications on Windows NTFull-text access may be available. Sign in or learn about subscription options.pp. 496
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