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2009 Asian Test Symposium

Nov. 23 2009 to Nov. 26 2009

Taichung

Table of Contents

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TutorialsFull-text access may be available. Sign in or learn about subscription options.pp. xviii-xix
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KeynotesFull-text access may be available. Sign in or learn about subscription options.pp. xx-xxiii
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[Copyright notice]Freely available from IEEE.pp. iv
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Table of contentsFreely available from IEEE.pp. v-xi
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Steering CommitteeFreely available from IEEE.pp. xiv
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Program CommitteeFreely available from IEEE.pp. xv-xvi
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list-reviewerFreely available from IEEE.pp. xvii
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Title Page iFreely available from IEEE.pp. i
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Title Page iiiFreely available from IEEE.pp. iii
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ForewordFreely available from IEEE.pp. xii
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Organizing CommitteeFreely available from IEEE.pp. xiii
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Best Paper Award of ATS 2008Freely available from IEEE.pp. xxiv
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Call for Papers of ATS 2010Freely available from IEEE.pp. xxv-xxv
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CA Based Built-In Self-Test Structure for SoCFull-text access may be available. Sign in or learn about subscription options.pp. 3-8
by Sukanta Das, Biplab K. Sikdar
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A Random Jitter RMS Estimation Technique for BIST ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 9-14
by Jae Wook Lee, Ji Hwan Chun, Jacob A. Abraham
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A Novel Seed Selection Algorithm for Test Time Reduction in BISTFull-text access may be available. Sign in or learn about subscription options.pp. 15-20
by Rupsa Chakraborty, Dipanwita Roy Chowdhury
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Logic BIST Architecture for System-Level Test and DiagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 21-26
by Jun Qian, Xingang Wang, Qinfu Yang, Fei Zhuang, Junbo Jia, Xiangfeng Li, Yuan Zuo, Jayanth Mekkoth, Jinsong Liu, Hao-Jan Chao, Shianling Wu, Huafeng Yang, Lizhen Yu, FeiFei Zhao, Laung-Terng Wang
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Fault Diagnosis under Transparent-ScanFull-text access may be available. Sign in or learn about subscription options.pp. 29-34
by Irith Pomeranz, Sudhakar M. Reddy
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Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG PatternsFull-text access may be available. Sign in or learn about subscription options.pp. 35-40
by Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen
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On Improving Diagnostic Test Generation for Scan Chain FailuresFull-text access may be available. Sign in or learn about subscription options.pp. 41-46
by Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy, Yu Huang
A FPGA-Based Reconfigurable Software Architecture for Highly Dependable SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 125-130
by Stefano Di Carlo, Paolo Prinetto, Alberto Scionti
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On Scan Chain Diagnosis for Intermittent FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 47-54
by Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, Erik Larsson
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Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction TechniqueFull-text access may be available. Sign in or learn about subscription options.pp. 57-62
by Jin-Fu Lin, Soon-Jyh Chang, Chih-Hao Huang
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Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial CoefficientsFull-text access may be available. Sign in or learn about subscription options.pp. 63-68
by Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
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Low Cost Dynamic Test Methodology for High Precision ΣΔ ADCsFull-text access may be available. Sign in or learn about subscription options.pp. 69-74
by S. Kook, Hyun Choi, Vishwanath Natarajan, Abhijit Chatterjee, Alfred Gomes, Shalahb Goyal, Le Jin
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Very-Low-Voltage Testing of Amorphous Silicon TFT CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 75-80
by Shiue-Tsung Shen, Wei-Hsiao Liu, En-Hua Ma, James Chien-Mo Li, I-Chun Cheng
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Scan Compression Implementation in Industrial Design - Case StudyFull-text access may be available. Sign in or learn about subscription options.pp. 83-84
by Dragon Hsu, Ron Press
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Calibration as a Functional Test: An ADC Case StudyFull-text access may be available. Sign in or learn about subscription options.pp. 85-86
by Hsiu-Ming Chang, Kuan-Yu Lin, Kwang-Ting Cheng
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Customized Algorithms for High Performance Memory Test in Advanced Technology NodeFull-text access may be available. Sign in or learn about subscription options.pp. 87-89
by Shomo Chen, Ning Huang, Ting-Pu Tai, Actel Niu
Speeding up SAT-Based ATPG Using Dynamic Clause ActivationFull-text access may be available. Sign in or learn about subscription options.pp. 177-182
by Stephan Eggersgluss, Daniel Tille, Rolf Drechsler
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A Practical DFT Approach for Complex Low Power DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 90-91
by Augusli Kifli, Y.W. Chen, Y.W. Tsay, K.C. Wu
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DFT Challenges in Next Generation Multi-media IPFull-text access may be available. Sign in or learn about subscription options.pp. 92-93
by Mukund Mittal, Subrangshu Das, S. Vishwanath
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Yield Ramp up by Scan Chain DiagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 94-95
by Feng-Ming Kuo, Yuan-Shih Chhen
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CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan TestingFull-text access may be available. Sign in or learn about subscription options.pp. 99-104
by K. Enokimoto, X. Wen, Y. Yamato, K. Miyase, H. Sone, S. Kajihara, M. Aso, H. Furukawa
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New Scheme of Reducing Shift and Capture Power Using the X-Filling MethodologyFull-text access may be available. Sign in or learn about subscription options.pp. 105-110
by Tsung-Tang Chen, Wei-Lin Li, Po-Han Wu, Jiann-Chyi Rau
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Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan TestingFull-text access may be available. Sign in or learn about subscription options.pp. 111-116
by Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chi-Wei Yu
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Low Overhead Time-Multiplexed Online Checking: A Case Study of An H.264 DecoderFull-text access may be available. Sign in or learn about subscription options.pp. 119-124
by Ming Gao, Kwang-Ting Cheng
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Using Non-trivial Logic Implications for Trace Buffer-Based Silicon DebugFull-text access may be available. Sign in or learn about subscription options.pp. 131-136
by Sandesh Prabhakar, Michael Hsiao
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A Post-Silicon Debug Support Using High-Level Design DescriptionFull-text access may be available. Sign in or learn about subscription options.pp. 137-142
by Yeonbok Lee, Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita
Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault TestingFull-text access may be available. Sign in or learn about subscription options.pp. 237-240
by K.G. Deepak, Robinson Reyna, Virendra Singh, Adit D. Singh
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A Low Overhead On-Chip Path Delay Measurement CircuitFull-text access may be available. Sign in or learn about subscription options.pp. 145-150
by Songwei Pei, Huawei Li, Xiaowei Li
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An Adaptive Test for Parametric Faults Based on Statistical Timing InformationFull-text access may be available. Sign in or learn about subscription options.pp. 151-156
by Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu
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A Delay Measurement Technique Using Signature RegistersFull-text access may be available. Sign in or learn about subscription options.pp. 157-162
by Kentaroh Katoh, Toru Tanabe, Haque Md Zahidul, Kazuteru Namba, Hideo Ito
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Functional Built-In Delay Binning and Calibration Mechanism for On-Chip at-Speed Self TestFull-text access may be available. Sign in or learn about subscription options.pp. 163-168
by Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng, Sih-Yan Li
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A Practical Approach to Threshold Test Generation for Error Tolerant CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 171-176
by Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue
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N-distinguishing Tests for Enhanced Defect DiagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 183-186
by Gang Chen, Janusz Rajski, Sudhakar Reddy, Irith Pomeranz
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Dynamic Compaction in SAT-Based ATPGFull-text access may be available. Sign in or learn about subscription options.pp. 187-190
by Alexander Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker
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SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area ImprovementFull-text access may be available. Sign in or learn about subscription options.pp. 193-199
by Mohammad Mirza-Aghatabar, Melvin A. Breuer, Sandeep K. Gupta
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Transaction Level Modeling and Design Space Exploration for SOC Test ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 200-205
by Chin-Yao Chang, Chih-Yuan Hsiao, Kuen-Jong Lee, Alan P. Su
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Efficient Software-Based Self-Test Methods for Embedded Digital Signal ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 206-211
by Jun-Jie Zhu, Wen-Ching Lin, Jheng-Hao Ye, Ming-Der Shieh
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Is Low Power Testing Necessary? What does the Test Industry Truly Need?Full-text access may be available. Sign in or learn about subscription options.pp. 215-216
by Anis Uzzaman
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A Scalable Scan Architecture for Godson-3 Multicore MicroprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 219-224
by Zichu Qi, Hui Liu, Xiangku Li, Da Wang, Yinhe Han, Huawei Li, Weiwu Hu
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Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application TimeFull-text access may be available. Sign in or learn about subscription options.pp. 225-230
by Michael S. Hsiao, Mainak Banga
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Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output ConstraintFull-text access may be available. Sign in or learn about subscription options.pp. 231-236
by Katherine Shu-Min Li, Yu-Chen Hung, Jr-Yang Huang
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BIST Driven Power Conscious Post-Manufacture Tuning of Wireless Transceiver Systems Using Hardware-Iterated Gradient SearchFull-text access may be available. Sign in or learn about subscription options.pp. 243-248
by Vishwanath Natarajan, Shyam Kumar Devarakond, Shreyas Sen, Abhijit Chatterjee
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Self-Calibrating Embedded RF Down-Conversion MixersFull-text access may be available. Sign in or learn about subscription options.pp. 249-254
by Abhilash Goyal, Madhavan Swaminathan, Abhijit Chatterjee
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A BIST Solution for the Functional Characterization of RF Systems Based on Envelope Response AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 255-260
by Manuel J. Barragán, Rafaella Fiorelli, Diego Vázquez, Adoración Rueda, José L. Huertas
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Exploiting Zero-Crossing for the Analysis of FM Modulated Analog/RF Signals Using Digital ATEFull-text access may be available. Sign in or learn about subscription options.pp. 261-266
by Nicolas Pous, Florence Azaïs, Laurent Latorre, Pascal Nouet, Jochen Rivoir
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IEEE 1500 Compatible Interconnect Test with Maximal Test ConcurrencyFull-text access may be available. Sign in or learn about subscription options.pp. 269-274
by Katherine Shu-Min Li, Yi-Yu Liao, Yuo-Wen Liu, Jr-Yang Huang
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Multiple-Core under Test Architecture for HOY Wireless Testing PlatformFull-text access may be available. Sign in or learn about subscription options.pp. 275-280
by Sung-Yu Chen, Ying-Yen Chen, Chun-Yu Yang, Jing-Jia Liou
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Partition Based SoC Test Scheduling with Thermal and Power Constraints under Deep Submicron TechnologiesFull-text access may be available. Sign in or learn about subscription options.pp. 281-286
by Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan
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Test Integration for SOC Supporting Very Low-Cost TestersFull-text access may be available. Sign in or learn about subscription options.pp. 287-292
by Chun-Chuan Chi, Chih-Yen Lo, Te-Wen Ko, Cheng-Wen Wu
A low-cost output response analyzer for the built-in-self-test Σ-Δ modulator based on the controlled sine wave fitting methodFull-text access may be available. Sign in or learn about subscription options.pp. 385-388
by Shao-Feng Hung, Hao-Chiao Hong, Sheng-Chuan Liang
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Why is Conventional ATPG Not Sufficient for Advanced Low Power Designs?Full-text access may be available. Sign in or learn about subscription options.pp. 295-300
by Krishna Chakravadhanula, Vivek Chickermane, Brion Keller, Patrick Gallagher, Anis Uzzaman
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New Class of Tests for Open Faults with Considering Adjacent LinesFull-text access may be available. Sign in or learn about subscription options.pp. 301-306
by Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Toshiyuki Tsutsumi, Hiroyuki Yotsuyanagi, Masaki Hashizume
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Test Pattern Selection and Customization Targeting Reduced Dynamic and Leakage Power ConsumptionFull-text access may be available. Sign in or learn about subscription options.pp. 307-312
by Subhadip Kundu, Krishna Kumar S., Santanu Chattopadhyay
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Deterministic Algorithms for ATPG under Leakage ConstraintsFull-text access may be available. Sign in or learn about subscription options.pp. 313-316
by Görschwin Fey
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Extended Selective Encoding of Scan Slices for Reducing Test Data and Test PowerFull-text access may be available. Sign in or learn about subscription options.pp. 319-324
by Jun Liu, Yinhe Han, Xiaowei Li
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A Multi-dimensional Pattern Run-Length Method for Test Data CompressionFull-text access may be available. Sign in or learn about subscription options.pp. 325-330
by Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chen-Lun Lee
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Bit-Operation-Based Seed Augmentation for LFSR Reseeding with High Defect CoverageFull-text access may be available. Sign in or learn about subscription options.pp. 331-336
by Hongxia Fang, Krishnendu Chakrabarty, Rubin Parekhji
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Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive?Full-text access may be available. Sign in or learn about subscription options.pp. 339
by Said Hamdioui
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A Non-Intrusive and Accurate Inspection Method for Segment Delay VariabilitiesFull-text access may be available. Sign in or learn about subscription options.pp. 343-348
by Ying-Yen Chen, Jing-Jia Liou
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Bridging Fault Diagnosis to Identify the Layer of Systematic DefectsFull-text access may be available. Sign in or learn about subscription options.pp. 349-354
by Po-Juei Chen, James Chien-Mo Li, Hsing Jasmine Chao
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Delay Fault Diagnosis in Sequential CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 355-360
by Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer
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A Partially-Exhaustive Gate Transition Fault ModelFull-text access may be available. Sign in or learn about subscription options.pp. 361-364
by Brion Keller, Dale Meehl, Anis Uzzaman, Richard Billings
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[Roster]Freely available from IEEE.pp. 466
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An On-Chip Integrator Leakage Characterization Technique and Its Application to Switched Capacitor Circuits TestingFull-text access may be available. Sign in or learn about subscription options.pp. 367-372
by Chen-Yuan Yang, Xuan-Lun Huang, Jiun-Lang Huang
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LFSR-Based Performance Characterization of Nonlinear Analog and Mixed-Signal CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 373-378
by Joonsung Park, Jaeyong Chung, Jacob A. Abraham
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A Jitter Characterizing BIST with Pulse-Amplifying TechniqueFull-text access may be available. Sign in or learn about subscription options.pp. 379-384
by An-Sheng Chao, Soon-Jyh Chang
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New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance FaultsFull-text access may be available. Sign in or learn about subscription options.pp. 391-396
by Ad J. van de Goor, Said Hamdioui, Georgi N. Gaydadjiev, Zaid Al-Ars
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Testability Exploration of 3-D RAMs and CAMsFull-text access may be available. Sign in or learn about subscription options.pp. 397-402
by Yu-Jen Huang, Jin-Fu Li
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Fault Diagnosis Using Test Primitives in Random Access MemoriesFull-text access may be available. Sign in or learn about subscription options.pp. 403-408
by Zaid Al-Ars, Said Hamdioui
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Test Generation for Designs with On-Chip Clock GeneratorsFull-text access may be available. Sign in or learn about subscription options.pp. 411-417
by Xijiang Lin, Mark Kassab
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On the Generation of Functional Test Programs for the Cache Replacement LogicFull-text access may be available. Sign in or learn about subscription options.pp. 418-423
by W.J. Perez H., D. Ravotto, E. Sanchez, M. Sonza Reorda, A. Tonda
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Compact Test Generation for Small-Delay Defects Using Testable-Path InformationFull-text access may be available. Sign in or learn about subscription options.pp. 424-429
by Dong Xiang, Boxue Yin, Krishendu Chakrabarty
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At-Speed Scan Test Method for the Timing Optimization and CalibrationFull-text access may be available. Sign in or learn about subscription options.pp. 430-433
by Kun-Han Tsai, Ruifeng Guo, Wu-Tung Cheng
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M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced DelayFull-text access may be available. Sign in or learn about subscription options.pp. 437-442
by Song Jin, Yinhe Han, Lei Zhang, Huawei Li, Xiaowei Li, Guihai Yan
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Analysis of Resistive Bridging Defects in a SynchronizerFull-text access may be available. Sign in or learn about subscription options.pp. 443-449
by Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang, Shianling Wu
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On-Chip TSV Testing for 3D IC before Bonding Using Sense AmplificationFull-text access may be available. Sign in or learn about subscription options.pp. 450-455
by Po-Yuan Chen, Cheng-Wen Wu, Ding-Ming Kwai
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Test Pattern Selection for Potentially Harmful Open Defects in Power Distribution NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 456-461
by Yubin Zhang, Lin Huang, Feng Yuan, Qiang Xu
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Author IndexFreely available from IEEE.pp. 462-465
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