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2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

Oct. 2 2019 to Oct. 4 2019

Noordwijk, Netherlands

ISBN: 978-1-7281-2260-1

Table of Contents

ForewordFreely available from IEEE.pp. 1-1
Simulating Wear-out Effects of Asymmetric Multicores at the Architecture LevelFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
Preventing Scan Attack through Test Response EncryptionFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
Protecting Large Word Size Memories against MCUs with 3-bit Burst Error CorrectionFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
CORE-VR: A Coherence and Reusability Aware Low Voltage Fault Tolerant Cache in MulticoreFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
Co-relation Scan Attack Analysis (COSAA) on AES: A Comprehensive ApproachFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
Reliability Evaluation of Polyphase-filter based Decimators Implemented on SRAM-FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
Developing a Configurable Fault Tolerant Multicore System for Optimized Sensor ProcessingFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
Scalable and Configurable Multi-Chip SRAM in a Package for Space ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
High Performance Memory RepairFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
Increasing the Efficiency and Efficacy of Selective-Hardening for Parallel ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
Understanding of GPU Architectural Vulnerability for Deep Learning WorkloadsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
Parity-Based Concurrent Error Detection Schemes for the ChaCha Stream CipherFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
Testing of In-Memory-Computing 8T SRAMsFull-text access may be available. Sign in or learn about subscription options.pp. 1-4
Predicting Single Event Effects in DRAMFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
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