Hardware/software codesign and system synthesis, International conference on
Oct. 22 2006 to Oct. 25 2006
Seoul, Korea
ISBN: 1-59593-370-0
Table of Contents
Session A1: HW/SW Design Exploration for Multimedia Applications
Session A1: HW/SW Design Exploration for Multimedia Applications
Session A1: HW/SW Design Exploration for Multimedia Applications
Session A1: HW/SW Design Exploration for Multimedia Applications
Session A1: HW/SW Design Exploration for Multimedia Applications
Session A2: Low Power Scheduling and Estimation Techniques
Session A2: Low Power Scheduling and Estimation Techniques
Session A2: Low Power Scheduling and Estimation Techniques
Session A3: System-Level Performance Issues
Session A3: System-Level Performance Issues
Session A4: Transaction-Level Modeling and Exploration
Session A4: Transaction-Level Modeling and Exploration
Session A4: Transaction-Level Modeling and Exploration
Session A4: Transaction-Level Modeling and Exploration
Session A5: Architecture and Modeling for Network-on-Chip
Session A5: Architecture and Modeling for Network-on-Chip
Session A5: Architecture and Modeling for Network-on-Chip
Session A6: Embedded Security and Reliability
Session A6: Embedded Security and Reliability
Session A7: Advanced Techniques for High-Level Synthesis and Physical Design
Session A7: Advanced Techniques for High-Level Synthesis and Physical Design
Session A7: Advanced Techniques for High-Level Synthesis and Physical Design
Session A8: Design Optimization for Network-on-Chip
Session A8: Design Optimization for Network-on-Chip
Session A9: Application-Specific Code Optimization
Session A9: Application-Specific Code Optimization
Session A9: Application-Specific Code Optimization
Session A9: Application-Specific Code Optimization
Special session A10: Programming Models for Multiprocessor Systems: From Supercomputing Programming to Multiprocessors on a Chip
Special session A10: Programming Models for Multiprocessor Systems: From Supercomputing Programming to Multiprocessors on a Chip
Special session A10: Programming Models for Multiprocessor Systems: From Supercomputing Programming to Multiprocessors on a Chip
Session A11: Simulation, Optimization, and Acceleration
Session A11: Simulation, Optimization, and Acceleration
Session A11: Simulation, Optimization, and Acceleration
Session A12: System-Level Design of MPSoC
Session A12: System-Level Design of MPSoC
Session A13: System-Level Optimization
Session A14: Architecture Exploration
Session A14: Architecture Exploration
Session A14: Architecture Exploration
Session A14: Architecture Exploration
Special Session A15: Industry Solutions to Emerging Embedded Systems
Session A16: Synthesis Techniques for Accelerators
Session A16: Synthesis Techniques for Accelerators
Session A16: Synthesis Techniques for Accelerators
Session A17: Communication Synthesis and Analysis for MPSoC
Session A17: Communication Synthesis and Analysis for MPSoC
Session A17: Communication Synthesis and Analysis for MPSoC