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Hardware/Software Co-Design, International Workshop on

Mar. 15 1998 to Mar. 18 1998

Seattle, Washington

ISSN: 1092-6100

ISBN: 0-8186-8442-9

Table of Contents

Message from the Workshop ChairsFreely available from IEEE.pp. vii
Chairs and Committee MembersFreely available from IEEE.pp. viii
Session 1: System-Level Modeling
An Analysis-Based Approach to Composition of Distributed Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 3
Session 1: System-Level Modeling
Combining Multiple Models of Computation for Scheduling and AllocationFull-text access may be available. Sign in or learn about subscription options.pp. 9
Session 1: System-Level Modeling
Modeling Reactive Systems in JavaFull-text access may be available. Sign in or learn about subscription options.pp. 15
Session 2: Partitioning
Energy-Conscious HW/SW-Partitioning of Embedded Systems: A Case Study on an MPEG-2 EncoderFull-text access may be available. Sign in or learn about subscription options.pp. 23
Session 2: Partitioning
HiPART: A New Hierarchical Semi-Interactive HW-/SW Partitioning Approach with Fast Debugging for Real-Time Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 29
Session 2: Partitioning
Towards Interprocess Communication and Interface Synthesis for a Heterogeneous Real-Time Rapid Prototyping EnvironmentFull-text access may be available. Sign in or learn about subscription options.pp. 35
Session 3: Communication and Interfaces Synthesis
Domain-Specific Interface Generation from Dataflow SpecificationsFull-text access may be available. Sign in or learn about subscription options.pp. 43
Session 3: Communication and Interfaces Synthesis
Communication Synthesis and HW/SW Integration for Embedded System DesignFull-text access may be available. Sign in or learn about subscription options.pp. 49
Session 3: Communication and Interfaces Synthesis
Communication Estimation for Hardware/Software CodesignFull-text access may be available. Sign in or learn about subscription options.pp. 55
Invited Talks
SmartBadges: A Wearable Computer and Communication SystemFull-text access may be available. Sign in or learn about subscription options.
Session 4: Co-Simulation
Software Timing Analysis Using HW/SW Cosimulation and Instruction Set SimulatorFull-text access may be available. Sign in or learn about subscription options.pp. 65
Session 4: Co-Simulation
Optimistic Distributed Timed Cosimulation Based on Thread Simulation ModelFull-text access may be available. Sign in or learn about subscription options.pp. 71
Session 4: Co-Simulation
Fast Dynamic Analysis of Complex HW/SW-Systems Based on Abstract State Machine ModelsFull-text access may be available. Sign in or learn about subscription options.pp. 77
Session 5: Scheduling
A Path Analysis Based Partitioning for Time Constrained Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 85
Session 5: Scheduling
Schedulability Analysis of Heterogeneous Systems for Performance Message Sequence ChartFull-text access may be available. Sign in or learn about subscription options.pp. 91
Session 5: Scheduling
TGFF Task Graphs for FreeFull-text access may be available. Sign in or learn about subscription options.pp. 97
Session 6: Case Studies
A Hardware/Software Prototyping Environment for Dynamically Reconfigurable Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 105
Session 6: Case Studies
Hardware/Software Co-design of an ATM Network Interface Card: A Case StudyFull-text access may be available. Sign in or learn about subscription options.pp. 111
Session 6: Case Studies
A Case Study on Modeling Shared Memory Access Effects During Performance Analysis of HW/SW SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 117
Session 7: System on Chip
The Construction of a Retargetable Simulator for Architecture TemplateFull-text access may be available. Sign in or learn about subscription options.pp. 125
Session 7: System on Chip
HDL Code Restructuring Using Timed Decision TablesFull-text access may be available. Sign in or learn about subscription options.pp. 131
Session 7: System on Chip
Instruction Subsetting: Trading Power for Programmability*Full-text access may be available. Sign in or learn about subscription options.
Session 8: System Level Modeling
RECOD: A Retiming Heuristic to Optimize Resource and Memory Utilization in HW/SW CodesignsFull-text access may be available. Sign in or learn about subscription options.pp. 139
Session 8: System Level Modeling
Memory Size Estimation for Multimedia ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 145
Session 8: System Level Modeling
Author IndexFreely available from IEEE.pp. 151
Session 8: System Level Modeling
* Papers not submitted for publication in proceedingsFull-text access may be available. Sign in or learn about subscription options.
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