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Hardware/Software Co-Design, International Workshop on

May 3 1999 to May 5 1999

Rome, Italy

ISBN: 1-58113-132-1

Table of Contents

Application-Specific Instruction-Set Processor (ASIP) Design Issues
Development of an Optimizing Compiler for a Fujitsu Fixed-Point Digital Signal ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 2
Application-Specific Instruction-Set Processor (ASIP) Design Issues
Instruction Set Selection for ASIP DesignFull-text access may be available. Sign in or learn about subscription options.pp. 7
Application-Specific Instruction-Set Processor (ASIP) Design Issues
Resource Constrained Dataflow Retiming Heuristics for VLIW ASIPsFull-text access may be available. Sign in or learn about subscription options.pp. 12
Application-Specific Instruction-Set Processor (ASIP) Design Issues
An ASIP Design Methodology for Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 17
Application-Specific Instruction-Set Processor (ASIP) Design Issues
Automatic Detection of Recurring Operation PatternsFull-text access may be available. Sign in or learn about subscription options.pp. 22
Application-Specific Instruction-Set Processor (ASIP) Design Issues
A Flexible Code Generation Framework for the Design of Application Specific Programmable ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 27
Case Studies
An MPEG-2 Decoder Case Study as a Driver for a System Level Design MethodologyFull-text access may be available. Sign in or learn about subscription options.pp. 33
Case Studies
Flexible Design of SPARC Cores: a Quantitative StudyFull-text access may be available. Sign in or learn about subscription options.pp. 43
Codesign Methodologies
Multilanguage Design of Heterogeneous SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 54
Codesign Methodologies
The Case for a Configure-and-Execute ParadigmFull-text access may be available. Sign in or learn about subscription options.pp. 59
Codesign Methodologies
Designing Digital Video Systems: Modeling and SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 64
Codesign Methodologies
Fast Prototyping: a Dystem Design Flow for Fast Design, Prototyping and Efficient IP ReuseFull-text access may be available. Sign in or learn about subscription options.pp. 69
Codesign Methodologies
Optimized Rapid Prototyping for Real-Time Embedded Heterogeneous MultiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 74
Codesign Methodologies
Using Codesign Techniques to Support Analog FunctionalityFull-text access may be available. Sign in or learn about subscription options.pp. 79
Hardware/Software Cosimulation and Timing Analysis
A Compilation-based Software Estimation Scheme for Hardware/Software Co-SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 85
Hardware/Software Cosimulation and Timing Analysis
A Probabilistic Performance Metric for Real-Time System DesignFull-text access may be available. Sign in or learn about subscription options.pp. 90
Hardware/Software Cosimulation and Timing Analysis
Iterative Cache Simulation of Embedded CPUs with Trace StrippingFull-text access may be available. Sign in or learn about subscription options.pp. 95
Hardware/Software Cosimulation and Timing Analysis
Optimizing Geographically Distributed Timed Cosimulation by Hierarchically Grouped MessagesFull-text access may be available. Sign in or learn about subscription options.pp. 100
Hardware/Software Cosimulation and Timing Analysis
Peer-based Multithreaded Executable Co-SpecificationFull-text access may be available. Sign in or learn about subscription options.pp. 105
Hardware/Software Cosimulation and Timing Analysis
Timing Coverification of Concurrent Embedded Real-Time SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 110
Hardware/Software Cosimulation and Timing Analysis
Worst-Case Analysis of Discrete Systems Based on Conditional AbstractionsFull-text access may be available. Sign in or learn about subscription options.pp. 115
Models for Codesign
A Unified Formal Model of ISA and FSMDFull-text access may be available. Sign in or learn about subscription options.pp. 121
Aspects on system-level designFull-text access may be available. Sign in or learn about subscription options.pp. 209-210
Models for Codesign
Co-Design Tool Construction Using APICESFull-text access may be available. Sign in or learn about subscription options.pp. 126
Models for Codesign
Graph based Communication Analysis for Hardware/Software CodesignFull-text access may be available. Sign in or learn about subscription options.pp. 131
Models for Codesign
System Synthesis Utilizing a Layered Functional ModelFull-text access may be available. Sign in or learn about subscription options.pp. 136
Software and Communication Issues
Communication Refinement in Video Systems on OhioFull-text access may be available. Sign in or learn about subscription options.pp. 142
Software and Communication Issues
Compiling Esterel into Sequential CodeFull-text access may be available. Sign in or learn about subscription options.pp. 147
Software and Communication Issues
Power Estimation for Architectural Exploration of HW/SW Communication on System-Level BusesFull-text access may be available. Sign in or learn about subscription options.pp. 152
Software and Communication Issues
Software Controlled Power ManagementFull-text access may be available. Sign in or learn about subscription options.pp. 157
Software and Communication Issues
A Statechart based HW/SW Codesign SystemFull-text access may be available. Sign in or learn about subscription options.pp. 162
Synthesis, Scheduling and Partitioning
3D Exploration of Software Schedules for DSP AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 168
Synthesis, Scheduling and Partitioning
Scheduling Hardware/Software Systems using Symbolic TechniquesFull-text access may be available. Sign in or learn about subscription options.pp. 173
Synthesis, Scheduling and Partitioning
Scheduling with Optimized Communication for Time-Triggered Embedded SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 178
Synthesis, Scheduling and Partitioning
A Hardware-Software Cosynthesis Technique based on Heterogeneous Multiprocessor SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 183
Synthesis, Scheduling and Partitioning
Embedded System Synthesis under Memory ConstraintsFull-text access may be available. Sign in or learn about subscription options.pp. 188
Synthesis, Scheduling and Partitioning
Overhead Effects in Real-Time Preemptive SchedulesFull-text access may be available. Sign in or learn about subscription options.pp. 193
Synthesis, Scheduling and Partitioning
System-Level Partitioning with UncertaintyFull-text access may be available. Sign in or learn about subscription options.pp. 198
Synthesis, Scheduling and Partitioning
Timing-Driven HW/SW Codesign based on Task Structuring and Process Timing SimulationFull-text access may be available. Sign in or learn about subscription options.pp. 203
Group Discussion Topic Summaries
Aspects on System-Level DesignFull-text access may be available. Sign in or learn about subscription options.pp. 209
Group Discussion Topic Summaries
How Standards will Enable Hardware/Software Co-DesignFull-text access may be available. Sign in or learn about subscription options.pp. 211
Group Discussion Topic Summaries
Author IndexFreely available from IEEE.pp. 213
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