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2012 IEEE COOL Chips XV

April 18 2012 to April 20 2012

Yokohama

Table of Contents

[Front matter]Freely available from IEEE.pp. 1-3
Message from the organizing committee chairFreely available from IEEE.pp. i-ii
by Hiroaki Kobayashi
Message from the advisory committee chairFreely available from IEEE.pp. iii-iii
by Tadao Nakamura
Message from the program committee chairsFreely available from IEEE.pp. iv-v
by Makoto Ikeda, Fumio Arakawa
List of the Committees membersFreely available from IEEE.pp. vi-viii
Final programFreely available from IEEE.pp. ix-xvi
Special session speaker's biographyFreely available from IEEE.pp. xvii-xviii
Keynote & invited speaker's biographyFreely available from IEEE.pp. xix-xxv
Supporting organizationFreely available from IEEE.pp. xxvi-xxvi
A simultaneous multithreading heterogeneous object recognition processor with machine learning based dynamic resource managementFull-text access may be available. Sign in or learn about subscription options.pp. 1-3
by Jinwook Oh, Gyeonghoon Kim, Junyoung Park, Injoon Hong, Seungjin Lee, Joo-Young Kim, Hoi-Jun Yoo
Dual-stage hardware architecture of on-line clustering with high-throughput parallel divider for low-power signal processingFull-text access may be available. Sign in or learn about subscription options.pp. 1-3
by Tse-Wei Chen, Makoto Ikeda
Poster prefaceFull-text access may be available. Sign in or learn about subscription options.pp. 1-2
by Koji Hashimoto
Panel discussionsFull-text access may be available. Sign in or learn about subscription options.pp. 1-2
A 5.184Gbps/ch through-chip interface and automated place-and-route design methodology for 3-D integration of 45nm CMOS processorsFull-text access may be available. Sign in or learn about subscription options.pp. 1-3
by Yasuhisa Shimazaki, Noriyuki Miura, Tadahiro Kuroda
Cool System scalable 3-D stacked heterogeneous Multi-Core / Multi-Chip architecture for ultra low-power digital TV applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 1-3
by Yukoh Matsumoto, Tomoyuki Morimoto, Michiya Hagimoto, Hiroyuki Uchida, Nobuyuki Hikichi, Fumito Imura, Hiroshi Nakagawa, Masahiro Aoyagi
Gate-level process variation offset technique by using dual voltage supplies to achieve near-threshold energy efficient operationFull-text access may be available. Sign in or learn about subscription options.pp. 1-3
by Benjamin Devlin, Makoto Ikeda, Kunihiro Asada
An area-efficient, standard-cell based on-chip NMOS and PMOS performance monitor for process variability compensationFull-text access may be available. Sign in or learn about subscription options.pp. 1-3
by Toshiyuki Yamagishi, Tatsuo Shiozawa, Koji Horisaki, Hiroyuki Hara, Yasuo Unekawa
Trade-off analysis of fine-grained power gating methods for functional units in a CPUFull-text access may be available. Sign in or learn about subscription options.pp. 1-3
by Weihan Wang, Yuya Ohta, Yoshifumi Ishii, Kimiyoshi Usami, Hideharu Amano
A media-oriented vector architectural extension with a high bandwidth cache systemFull-text access may be available. Sign in or learn about subscription options.pp. 1-3
by Ye Gao, Naoki Shoji, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi
Dependable Responsive Multithreaded Processor for distributed real-time systemsFull-text access may be available. Sign in or learn about subscription options.pp. 1-3
by Kazutoshi Suito, Kei Fujii, Hiroki Matsutani, Nobuyuki Yamasaki
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