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2009 Design, Automation & Test in Europe Conference & Exhibition (DATE'09)

April 20 2009 to April 24 2009

Nice

Table of Contents

StartFreely available from IEEE.
ReviewersFreely available from IEEE.pp. xxxix-xlii
2009 EDAA PhD forum at DATEFreely available from IEEE.pp. l-li
Has anything changed in electronic design since 1983?Full-text access may be available. Sign in or learn about subscription options.pp. 1
by Mike Muller
Embedded systems design - Scientific challenges and work directionsFull-text access may be available. Sign in or learn about subscription options.
by Joseph Sifakis
A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chipFull-text access may be available. Sign in or learn about subscription options.
by Huaxi Gu, Jiang Xu, Wei Zhang
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chipsFull-text access may be available. Sign in or learn about subscription options.pp. 9-14
by Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli
User-centric design space exploration for heterogeneous Network-on-Chip platformsFull-text access may be available. Sign in or learn about subscription options.
by Chen-Ling Chou, Radu Marculescu
A highly resilient routing algorithm for fault-tolerant NoCsFull-text access may be available. Sign in or learn about subscription options.pp. 21-26
by David Fick, Andrew DeOrio, Gregory Chen, Valeria Bertacco, Dennis Sylvester, David Blaauw
Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architectureFull-text access may be available. Sign in or learn about subscription options.pp. 27-32
by Sean Whitty, Henning Sahlbach, Rolf Ernst, Wolfram Putzke-Roming
An ILP formulation for task mapping and scheduling on multi-core architecturesFull-text access may be available. Sign in or learn about subscription options.
by Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tughrul Arslan
DPR in high energy physicsFull-text access may be available. Sign in or learn about subscription options.pp. 39-44
by Wenxue Gao, Andreas Kugel, Reinhard Manner, Norbert Abel, Nick Meier, Udo Kebschull
A flexible layered architecture for accurate digital baseband algorithm development and verificationFull-text access may be available. Sign in or learn about subscription options.pp. 45-50
by Amirhossein Alimohammad, Saeed F. Fard, Bruce F. Cockburn
Lifetime reliability-aware task allocation and scheduling for MPSoC platformsFull-text access may be available. Sign in or learn about subscription options.
by Lin Huang, Feng Yuan, Qiang Xu
Integrated scheduling and synthesis of control applications on distributed embedded systemsFull-text access may be available. Sign in or learn about subscription options.pp. 57-62
by Soheil Samii, Anton Cervin, Petru Eles, Zebo Peng
Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitudeFull-text access may be available. Sign in or learn about subscription options.
by Chengmo Yang, Alex Orailoglu
Pipelined data parallel task mapping/scheduling technique for MPSoCFull-text access may be available. Sign in or learn about subscription options.
by Hoeseok Yang, Soonhoi Ha
Joint logic restructuring and pin reordering against NBTI-induced performance degradationFull-text access may be available. Sign in or learn about subscription options.
by Kai-Chiang Wu, Diana Marculescu
A self-adaptive system architecture to address transistor agingFull-text access may be available. Sign in or learn about subscription options.pp. 81-86
by Omer Khan, Sandip Kundu
Masking timing errors on speed-paths in logic circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 87-92
by Mihir R. Choudhury, Kartik Mohanram
WCRT algebra and interfaces for esterel-style synchronous processingFull-text access may be available. Sign in or learn about subscription options.pp. 93-98
by Michael Mendler, Reinhard von Hanxleden, Claus Traulsen
Reliable mode changes in real-time systems with fixed priority or EDF schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 99-104
by Nikolay Stoimenov, Simon Perathoner, Lothar Thiele
Improved worst-case response-time calculations by upper-bound conditionsFull-text access may be available. Sign in or learn about subscription options.pp. 105-110
by Victor Pollex, Steffen Kollmann, Karsten Albers, Frank Slomka
A generalized scheduling approach for dynamic dataflow applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 111-116
by William Plishker, Nimish Sane, Shuvra S. Bhattacharyya
Optimizing data flow graphs to minimize hardware implementationFull-text access may be available. Sign in or learn about subscription options.
by D. Gomez-Prado, Q. Ren, M. Ciesielski, J. Guillot, E. Boutillon
Multi-clock Soc design using protocol conversionFull-text access may be available. Sign in or learn about subscription options.pp. 123-128
by Roopak Sinha, Partha S. Roop, Samik Basu, Zoran Salcic
A formal approach to design space exploration of protocol convertersFull-text access may be available. Sign in or learn about subscription options.pp. 129-134
by Karin Avnit, Arcot Sowmya
Model-based synthesis and optimization of static multi-rate image processing algorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 135-140
by Joachim Keinert, Hritam Dutta, Frank Hannig, Christian Haubelt, Jurgen Teich
Panel session - Consolidation, a modern “Moor of Venice” taleFreely available from IEEE.pp. 141-141
by M. Casale-Rossi, G. De Micheli
Variation resilient adaptive controller for subthreshold circuitsFull-text access may be available. Sign in or learn about subscription options.
by Biswajit Mishra, Bashir M. Al-Hashimi, Mark Zwolinski
Minimization of NBTI performance degradation using internal node controlFull-text access may be available. Sign in or learn about subscription options.pp. 148-153
by David R. Bild, Gregory E. Bok, Robert P. Dick
Physically clustered forward body biasing for variability compensation in nanometer CMOS designFull-text access may be available. Sign in or learn about subscription options.pp. 154-159
by Ashoka Sathanur, Antonio Pullini, Luca Benini, Giovanni De Micheli, Enrico Macii
An event-guided approach to reducing voltage noise in processorsFull-text access may be available. Sign in or learn about subscription options.
by Meeta S. Gupta, Vijay Janapa Reddi, Glenn Holloway, Gu-Yeon Wei, David M. Brooks
Design and implementation of a database filter for BLAST accelerationFull-text access may be available. Sign in or learn about subscription options.pp. 166-171
by Panagiotis Afratis, Constantinos Galanakis, Euripides Sotiriades, Georgios-Grigorios Mplemenos, Grigorios Chrysos, Ioannis Papaefstathiou, Dionisios Pnevmatikatos
A software-supported methodology for exploring interconnection architectures targeting 3-D FPGAsFull-text access may be available. Sign in or learn about subscription options.
by Kostas Siozios, Vasilis F. Pavlidis, Dimitrios Soudris
Priority-based packet communication on a bus-shaped structure for FPGA-systemsFull-text access may be available. Sign in or learn about subscription options.pp. 178-183
by Oliver Sander, Benjamin Glas, Christoph Roth, Jurgen Becker, Klaus D. Muller-Glaser
Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processorFull-text access may be available. Sign in or learn about subscription options.pp. 184-189
by Syed Zahid Ahmed, Julien Eydoux, Laurent Rouge, Jean-Baptiste Cuelle, Gilles Sassatelli, Lionel Torres
Functional qualification of TLM verificationFull-text access may be available. Sign in or learn about subscription options.pp. 190-195
by Nicola Bombieri, Franco Fummi, Graziano Pravadelli, Mark Hampton, Florian Letombe
Solver technology for system-level to RTL equivalence checkingFull-text access may be available. Sign in or learn about subscription options.
by Alfred Koelbl, Reily Jacoby, Himanshu Jain, Carl Pixley
A high-level debug environment for communication-centric debugFull-text access may be available. Sign in or learn about subscription options.pp. 202-207
by Kees Goossens, Bart Vermeulen, Ashkan Beyranvand Nejad
Cache aware compression for processor debug supportFull-text access may be available. Sign in or learn about subscription options.pp. 208-213
by Anant Vishnoi, Preeti Ranjan Panda, M. Balakrishnan
Fault insertion testing of a novel CPLD-based fail-safe systemFull-text access may be available. Sign in or learn about subscription options.
by Gerhard Griessnig, Roland Mader, Christian Steger, Reinhold Weiss
Test architecture design and optimization for three-dimensional SoCsFull-text access may be available. Sign in or learn about subscription options.
by Li Jiang, Lin Huang, Qiang Xu
A co-design approach for embedded system modeling and code generation with UML and MARTEFull-text access may be available. Sign in or learn about subscription options.
by Jorgiano Vidal, Florent de Lamotte, Guy Gogniat, Philippe Soulard, Jean-Philippe Diguet
Componentizing hardware/software interface designFull-text access may be available. Sign in or learn about subscription options.
by Kecheng Hao, Fei Xie
A UML frontend for IP-XACT-based IP managementFull-text access may be available. Sign in or learn about subscription options.pp. 238-243
by Tim Schattkowsky, Tao Xie, Wolfgang Mueller
Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 244-249
by Tero Arpinen, Tapio Koskinen, Erno Salminen, Timo D. Hamalainen, Marko Hannikainen
Aelite: A flit-synchronous Network on Chip with composable and predictable servicesFull-text access may be available. Sign in or learn about subscription options.
by Andreas Hansson, Mahesh Subburaman, Kees Goossens
Configurable links for runtime adaptive on-chip communicationFull-text access may be available. Sign in or learn about subscription options.pp. 256-261
by Mohammad Abdullah Al Faruque, Thomas Ebi, Jorg Henkel
Synthesis of low-overhead configurable source routing tables for network interfacesFull-text access may be available. Sign in or learn about subscription options.
by Igor Loi, Federico Angiolini, Luca Benini
SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systemsFull-text access may be available. Sign in or learn about subscription options.pp. 268-273
by Abelardo Jara-Berrocal, Ann Gordon-Ross
Analog layout synthesis - Recent advances in topological approachesFreely available from IEEE.
by H. Graeb, F. Balasa, R. Castro-Lopez, Y.-W. Chang, F.V. Fernandez, P.-H. Lin, M. Strasser
An accurate interconnect thermal model using equivalent transmission line circuitFull-text access may be available. Sign in or learn about subscription options.
by Baohua Wang, Pinaki Mazumder
Analogue mixed signal simulation using spice and SystemCFull-text access may be available. Sign in or learn about subscription options.
by Tobias Kirchner, Nico Bannow, Christoph Grimm
Reliability aware through silicon via planning for 3D stacked ICsFull-text access may be available. Sign in or learn about subscription options.pp. 288-291
by Amirali Shayan, Xiang Hu, He Peng, Chung-Kuan Cheng, Wenjian Yu, Mikhail Popovich, Thomas Toms, Xiaoming Chen
A study on placement of post silicon clock tuning buffers for mitigating impact of process variationFull-text access may be available. Sign in or learn about subscription options.pp. 292-295
by Kelageri Nagaraj, Sandip Kundu
Analysis and optimization of NBTI induced clock skew in gated clock treesFull-text access may be available. Sign in or learn about subscription options.
by Ashutosh Chakraborty, Gokul Ganesan, Anand Rajaram, David Z. Pan
Bitstream relocation with local clock domains for partially reconfigurable FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 300-303
by Adam Flynn, Ann Gordon-Ross, Alan D. George
Parallel transistor level full-chip circuit simulationFull-text access may be available. Sign in or learn about subscription options.
by He Peng, Chung-Kuan Cheng
Performance-driven dual-rail insertion for chip-level pre-fabricated designFull-text access may be available. Sign in or learn about subscription options.
by Fu-Wei Chen, Yi-Yu Liu
Simulation framework for early phase exploration of SDR platforms: A case study of platform dimensioningFull-text access may be available. Sign in or learn about subscription options.pp. 312-315
by Martin Trautmann, Stylianos Mamagkakis, Bruno Bougard, Jeroen Declerck, Erik Umans, Antoine Dejonghe, Liesbet Van der Perre, Francky Catthoor
Fast and accurate protocol specific bus modeling using TLM 2.0Full-text access may be available. Sign in or learn about subscription options.
by H.W.M. van Moll, H. Corporaal, V. Reyes, M. Boonen
Incorporating graceful degradation into embedded system designFull-text access may be available. Sign in or learn about subscription options.
by Michael Glass, Martin Lukasiewycz, Christian Haubelt, Jurgen Teich
Rewiring using IRredundancy Removal and AdditionFull-text access may be available. Sign in or learn about subscription options.
by Chun-Chi Lin, Chun-Yao Wang
Gate replacement techniques for simultaneous leakage and aging optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 328-333
by Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang
Enabling concurrent clock and power gating in an industrial design flowFull-text access may be available. Sign in or learn about subscription options.
by Leticia Bolzani, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino
TRAM: A tool for Temperature and Reliability Aware Memory DesignFull-text access may be available. Sign in or learn about subscription options.
by Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi Kurdahi, Ahmed Eltawil, Kamal Khouri, Magdy Abadir
Aircraft integration real-time simulator modeling with AADL for architecture tradeoffsFull-text access may be available. Sign in or learn about subscription options.
by Jean Casteres, Tovo Ramaherirariny
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable ChipsFull-text access may be available. Sign in or learn about subscription options.pp. 352-357
by M. Sonza Reorda, M. Violante, C. Meinhardt, R. Reis
Communication minimization for in-network processing in body sensor networks: A buffer assignment techniqueFull-text access may be available. Sign in or learn about subscription options.pp. 358-363
by Hassan Ghasemzadeh, Nisha Jain, Marco Sgroi, Roozbeh Jafari
A MEMS reconfigurable quad-band Class-E Power Amplifier for GSM standardFull-text access may be available. Sign in or learn about subscription options.
by Luca Larcher, Riccardo Brama, Marcello Ganzerli, Jacopo Iannacci, Marco Bedani, Antonio Gnudi
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharingFull-text access may be available. Sign in or learn about subscription options.
by J. A. Diaz-Madrid, H. Neubauer, H. Hauer, G. Domenech-Asensi, R. Ruiz-Merino
PANEL SESSION - Is the second wave of HLS the one industry will surf on?Freely available from IEEE.pp. 374-374
by L. Le Toumelin
Analyzing the impact of process variations on parametric measurements: Novel models and applicationsFull-text access may be available. Sign in or learn about subscription options.
by Sherief Reda, Sani R. Nassif
On linewidth-based yield analysis for nanometer lithographyFull-text access may be available. Sign in or learn about subscription options.
by Aswin Sreedhar, Sandip Kundu
Impact of voltage scaling on nanoscale SRAM reliabilityFull-text access may be available. Sign in or learn about subscription options.
by Vikas Chandra, Robert Aitken
A file-system-aware FTL design for flash-memory storage systemsFull-text access may be available. Sign in or learn about subscription options.
by Po-Liang Wu, Yuan-Hao Chang, Tei-Wei Kuo
FSAF: File system aware flash translation layer for NAND Flash MemoriesFull-text access may be available. Sign in or learn about subscription options.
by Sai Krishna Mylavarapu, Siddharth Choudhuri, Aviral Shrivastava, Jongeun Lee, Tony Givargis
A set-based mapping strategy for flash-memory reliability enhancementFull-text access may be available. Sign in or learn about subscription options.
by Yuan-Sheng Chu, Jen-Wei Hsieh, Yuan-Hao Chang, Tei-Wei Kuo
Energy efficient multiprocessor task scheduling under input-dependent variationFull-text access may be available. Sign in or learn about subscription options.
by Jason Cong, Karthik Gururaj
Program phase and runtime distribution-aware online DVFS for combined Vdd/Vbb scalingFull-text access may be available. Sign in or learn about subscription options.
by Jungsoo Kim, Sungjoo Yoo, Chong-Min Kyung
ORION 2.0: A fast and accurate NoC power and area model for early-stage design space explorationFull-text access may be available. Sign in or learn about subscription options.
by Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi
Panel session - Open source hardware IP, are you serious?Freely available from IEEE.pp. 429-429
by P. Parrish
HOT TOPIC - Concurrent SoC development and end-to-end planningFull-text access may be available. Sign in or learn about subscription options.
by L. Anghel
Nano-electronics challenge chip designers meet real nano-electronics in 2010s?Full-text access may be available. Sign in or learn about subscription options.
by Shinobu Fujita
MTJ-based nonvolatile logic-in-memory circuit, future prospects and issuesFull-text access may be available. Sign in or learn about subscription options.
by Shoun Matsunaga, Jun Hayakawa, Shoji Ikeda, Katsuya Miura, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect TransistorsFull-text access may be available. Sign in or learn about subscription options.pp. 436-441
by Subhasish Mitra, Jie Zhang, Nishant Patil, Hai Wei
Reconfigurable circuit design with nanomaterialsFull-text access may be available. Sign in or learn about subscription options.
by Chen Dong, Scott Chilstedt, Deming Chen
An architecture for secure software defined radioFull-text access may be available. Sign in or learn about subscription options.
by Chunxiao Li, Anand Raghunathan, Niraj K. Jha
Optimizing the HW/SW boundary of an ECC SoC design using control hierarchy and distributed storageFull-text access may be available. Sign in or learn about subscription options.
by Xu Guo, Patrick Schaumont
Hardware aging-based software meteringFull-text access may be available. Sign in or learn about subscription options.
by Foad Dabiri, Miodrag Potkonjak
On-chip communication architecture exploration for processor-pool-based MPSoCFull-text access may be available. Sign in or learn about subscription options.
by Young-Pyo Joo, Sungchan Kim, Soonhoi Ha
Combined system synthesis and communication architecture exploration for MPSoCsFull-text access may be available. Sign in or learn about subscription options.
by Martin Lukasiewycz, Martin Streubuhr, Michael Glass, Christian Haubelt, Jurgen Teich
UMTS MPSoC design evaluation using a system level design frameworkFull-text access may be available. Sign in or learn about subscription options.pp. 478-483
by Douglas Densmore, Alena Simalatsar, Abhijit Davare, Roberto Passerone, Alberto Sangiovanni-Vincentelli
Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chipsFull-text access may be available. Sign in or learn about subscription options.
by Mikael Vayrynen, Virendra Singh, Erik Larsson
Improving yield and reliability of chip multiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 490-495
by Abhisek Pan, Omer Khan, Sandip Kundu
A unified online Fault Detection scheme via checking of Stability ViolationFull-text access may be available. Sign in or learn about subscription options.
by Guihai Yan, Yinhe Han, Xiaowei Li
Statistical fault injection: Quantified error and confidenceFull-text access may be available. Sign in or learn about subscription options.pp. 502-506
by R. Leveugle, A. Calvez, P. Maistri, P. Vanhauwaert
KAST: K-associative sector translation for NAND flash memory in real-time systemsFull-text access may be available. Sign in or learn about subscription options.
by Hyunjin Cho, Dongkun Shin, Young Ik Eom
White box performance analysis considering static non-preemptive software schedulingFull-text access may be available. Sign in or learn about subscription options.
by Alexander Viehl, Michael Pressler, Oliver Bringmann, Wolfgang Rosenstiel
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