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Proceedings
DDECS
DDECS 2011
Generate Citations
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
Apr. 13 2011 to Apr. 15 2011
Cottbus Germany
ISBN: 978-1-4244-9755-3
Table of Contents
[Copyright notice]
Freely available from IEEE.
pp. 1-1
Foreword to the 14
th
IEEE DDECS symposium
Freely available from IEEE.
pp. 1-1
by
Rolf Kraemer
,
Adam Pawlak
,
Andreas Steininger
,
Mario Schölzel
,
Jaan Raik
,
Heinrich T. Vierhaus
Design technology and the cloud
Freely available from IEEE.
pp. 1-1
by
Raul Camposano
Cost effective scaling to 22nm and below technology nodes
Freely available from IEEE.
pp. 2-2
by
Andrzej J. Strojwas
Future of EDA: Usual suspect or silent hero for successful semiconductor business?
Freely available from IEEE.
pp. 3-3
by
Jürgen Alt
SiGe BiCMOS platform - baseline technology for More Than Moore process module integration
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pp. 4-4
by
Bernd Tillack
Testing and design-for-testability solutions for 3D integrated circuits
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pp. 5-5
by
Krishnendu Chakrabarty
Introduction to the SystemC AMS extension standard
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pp. 6-8
by
Karsten Einwich
Small scale energy harvesting - principles, practices and future trends
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pp. 9-9
by
Dong S. Ha
Conversion and interfacing techniques for asynchronous circuits
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pp. 11-16
by
Markus Ferringer
A system-level platform for dependability enhancement and its analysis for mixed-signal SoCs
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pp. 17-22
by
Muhammad A. Khan
,
Hans G. Kerkhoff
Dual use of power lines for data communications in microprocessors
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pp. 23-28
by
Vipul Chawla
,
Dong Sam Ha
PVT tolerant LC-VCO in 90 nm CMOS technology for GPS/Galileo applications
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pp. 29-34
by
Krzysztof Siwiec
,
Tomasz Borejko
,
Witold A. Pleskacz
Design-for-Test method for high-speed ADCs: Behavioral description and optimization
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pp. 35-40
by
Y. Lechuga
,
R. Mozuelos
,
M. Martínez
,
S. Bracho
High performance adaptive sensor interface design through model based estimation of analog non-idealities
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pp. 41-46
by
Sumit Adhikari
,
Muhammad Farooq
,
Jan Haase
,
Christoph Grimm
Cost-efficient 130nm TSMC Forward Transform and Quantization for H.264/AVC encoders
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pp. 47-52
by
Xuan-Tu Tran
,
Van-Huan Tran
Towards an unified IP verification and robustness analysis platform
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pp. 53-58
by
David Hély
,
Vincent Beroulle
,
Feng Lu
,
José Ramon Oya Garcia
An example of DISPLAY-CTRL IP Component verification in SCE-MI based emulation platform
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pp. 59-63
by
Włodzimierz Wrona
,
Paweł Duc
,
Łukasz Barcik
,
Wojciech Pietrasina
An analog perspective on device reliability in 32nm high-κ metal gate technology
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pp. 65-70
by
Florian Raoul Chouard
,
Shailesh More
,
Michael Fulde
,
Doris Schmitt-Landsiedel
Increasing the efficiency of analog OBIST using on-chip compensation of technology variations
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pp. 71-74
by
Daniel Arbet
,
Juraj Brenkuš
,
Gábor Gyepes
,
Viera Stopjaková
A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations
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pp. 75-79
by
Michał Łukaszewicz
,
Tomasz Borejko
,
Witold A. Pleskacz
Defect-oriented module-level fault diagnosis in digital circuits
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pp. 81-86
by
Sergei Kostin
,
Raimund Ubar
,
Jaan Raik
Efficient diagnostics algorithms for regular computing structures
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pp. 87-92
by
Miroslav Mánik
,
Elena Gramatová
SAT-based analysis of sensitisable paths
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pp. 93-98
by
Matthias Sauer
,
Alexander Czutro
,
Tobias Schubert
,
Stefan Hillebrecht
,
Ilia Polian
,
Bernd Becker
Wireless wafer-level testing of integrated circuits via capacitively-coupled channels
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pp. 99-104
by
Dae Young Lee
,
David D. Wentzloff
,
John P. Hayes
Optimal number and placement of Through Silicon Vias in 3D Network-on-Chip
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pp. 105-110
by
Thomas Canhao Xu
,
Pasi Liljeberg
,
Hannu Tenhunen
Decoupling capacitance boosting for on-chip resonant supply noise reduction
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pp. 111-114
by
Jinmyoung Kim
,
Toru Nakura
,
Hidehiro Takata
,
Koichiro Ishibashi
,
Makoto Ikeda
,
Kunihiro Asada
An all-digital on-chip PMOS and NMOS process variability monitor utilizing shared buffer ring and ring oscillator
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pp. 115-120
by
Tetsuya Iizuka
,
Kunihiro Asada
Low-complexity integrated circuit aging monitor
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pp. 121-125
by
Aleksandar Simevski
,
Rolf Kraemer
,
Milos Krstic
A 5Gb/s equalizer for USB 3.0 receiver in 65 nm CMOS technology
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pp. 131-134
by
Jakub Kopanski
,
Witold A. Pleskacz
,
Dariusz Pienkowski
Fault tolerance of SRAM-based FPGA via configuration frames
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pp. 139-142
by
Farid Lahrach
,
Abderrahim Doumar
,
Eric Châtelet
A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors
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pp. 143-146
by
Markus Ulbricht
,
Mario Schölzel
,
Tobias Koal
,
Heinrich Theodor Vierhaus
A chaos-based pseudo-random bit generator implemented in FPGA device
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pp. 151-154
by
Pawel Dabal
,
Ryszard Pelka
Software defined radio - design and implementation of complete platform
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pp. 155-158
by
P. Pawłowski
,
A. Dąbrowski
,
P. Skrzypek
,
P. Roszak
,
A. Pałejko
,
T. Walenciak
,
M. Mor
Influence of parasitic memory effect on single-cell faults in SRAMs
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pp. 159-162
by
Sandra Irobi
,
Zaid Al-Ars
,
Said Hamdioui
,
Michel Renovell
Behavioral model of TRNG based on oscillator rings implemented in FPGA
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pp. 163-166
by
Knut Wold
,
Slobodan Petrović
Hybrid Simulation Environment for rapid MSP430 system design test and validation using MSPsim and SystemC
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pp. 167-170
by
Oliver Stecklina
,
Frank Vater
,
Thomas Basmer
,
Erik Bergmann
,
Hannes Menzel
Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations
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pp. 175-178
by
Tsuyoshi Iwagaki
,
Kewal K. Saluja
Decomposition of multi-output logic function in Reed-Muller spectral domain
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pp. 179-182
by
Stefan Kołodziński
,
Edward Hrynkiewicz
Functional enhancements of TMR for power efficient and error resilient ASIC designs
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pp. 183-188
by
Hagen Sämrow
,
Claas Cornelius
,
Philipp Gorski
,
Jakob Salzmann
,
Andreas Tockhorn
,
Dirk Timmermann
A study of path delay variations in the presence of uncorrelated power and ground supply noise
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pp. 189-194
by
A. Todri
,
A. Bosio
,
L. Dilillo
,
P. Girard
,
S. Pravossoudovitch
,
A. Virazel
Muller C-elements based on minority-3 functions for ultra low voltage supplies
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pp. 195-200
by
Hans Kristian Otnes Berge
,
Amir Hasanbegović
,
Snorre Aunet
Power consumption traces realignment to improve differential power analysis
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pp. 201-206
by
G. Di Natale
,
M.L. Flottes
,
B. Rouzeyre
,
M. Valka
,
D. Real
Fault injection analysis of transient faults in clustered VLIW processors
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pp. 207-212
by
L. Sterpone
,
D. Sabena
,
S. Campagna
,
M. Sonza Reorda
Implementation of Selective Fault Tolerance with conventional synthesis tools
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pp. 213-218
by
Michael Augustin
,
Michael Gössel
,
Rolf Kraemer
Optimal spare utilization for reliability and mean lifetime improvement of logic built-in self-repair
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pp. 219-224
by
Tobias Koal
,
Heinrich Theodor Vierhaus
An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors
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pp. 225-230
by
Abdelmajid Bouajila
,
Johannes Zeppenfeld
,
Walter Stechele
,
Andreas Herkersdorf
Hardware architecture for packet classification with prefix coloring
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pp. 231-236
by
Viktor Puš
,
Michal Kajan
,
Jan KoŸenek
Communication modelling and synthesis for NoC-based systems with real-time constraints
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pp. 237-242
by
Mihkel Tagel
,
Peeter Ellervee
,
Thomas Hollstein
,
Gert Jervan
Optimization of message encryption for distributed embedded systems with real-time constraints
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pp. 243-248
by
Ke Jiang
,
Petru Eles
,
Zebo Peng
Manufacturing variability analysis in Carbon Nanotube Technology: A comparison with bulk CMOS in 6T SRAM scenario
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pp. 249-254
by
Carmen García
,
Antonio Rubio
Characterization of digital cells for statistical test
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pp. 255-260
by
Fabian Hopsch
,
Michael Lindig
,
Bernd Straube
,
Wolfgang Vermeiren
A variation-aware adaptive voltage scaling technique based on in-situ delay monitoring
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pp. 261-266
by
Martin Wirnshofer
,
Leonhard Heiß
,
Georg Georgakos
,
Doris Schmitt-Landsiedel
Receiver OEIC using a bipolar translinear loop
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pp. 267-270
by
A. Marchlewski
,
H. Zimmermann
,
I. Jonak-Auer
,
E. Wachmann
DODT: Increasing requirements formalism using domain ontologies for improved embedded systems development
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pp. 271-274
by
Stefan Farfeleder
,
Thomas Moser
,
Andreas Krall
,
Tor Stålhane
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Herbert Zojer
,
Christian Panis
Abstract modeling and simulation based selective estimation
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pp. 275-278
by
Yaseen Zaidi
,
Sumit Adhikari
,
Christoph Grimm
Fast just-in-time translated simulator for ASIP design
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pp. 279-282
by
Zdeněk Přikryl
,
Jakub Křoustek
,
Tomáš Hruška
,
Dušan Kolář
CAD tool for PLL Design
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pp. 283-286
by
Krzysztof Siwiec
,
Tomasz Borejko
,
Witold A. Pleskacz
Verification of JPEG2000 encoder based on rate and distortion curve analysis
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pp. 289-292
by
Damian Modrzyk
,
Michał Staworko
Failure probability of SRAM-FPGA systems with Stochastic Activity Networks
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pp. 293-296
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Cinzia Bernardeschi
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Luca Cassano
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Andrea Domenici
Improving performance of robust Self Adaptive Caches by optimizing the switching algorithm
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pp. 297-300
by
Liviu Agnola
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Mircea Vlăduţiu
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Mihai Udrescu
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Lucian Prodan
Sample synchronization of multiple multiplexed DA and AD converters in FPGAs
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pp. 301-304
by
Thilo Ohlemueller
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Markus Petri
Hardware efficient design of Variable Length FFT Processor
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pp. 309-312
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Vinay Gautam
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Kailash Chandra Ray
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Pauline Haddow1
High-performance hardware accelerators for sorting and managing priorities
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pp. 313-318
by
Valery Sklyarov
,
Iouliia Skliarova
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Dmitri Mihhailov
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Alexander Sudnitson
Precise IPv4/IPv6 packet generator based on NetCOPE platform
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pp. 319-324
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Jiří Matoušek
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Pavol Korček
Effective hash-based IPv6 longest prefix match
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pp. 325-328
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Jiří Tobola
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Jan Kořenek
Stacking order impact on overall 3D die-to-wafer Stacked-IC cost
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pp. 335-340
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Mottaqiallah Taouil
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Said Hamdioui
A memetic algorithm for computing 3D capacitance in multiconductor VLSI circuits
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pp. 341-346
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Yiorgos I. Bontzios
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Michael G. Dimopoulos
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Alkis A. Hatzopoulos
Optimized embedded memory diagnosis
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pp. 347-352
by
M. de Carvalho
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P. Bernardi
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M. Sonza Reorda
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N. Campanelli
,
T. Kerekes
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D. Appello
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M. Barone
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V. Tancorre
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M. Terzi
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling
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pp. 353-358
by
L. B. Zordan
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A. Bosio
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L. Dilillo
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P. Girard
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S. Pravossoudovitch
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A. Virazel
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N. Badereddine
On using a SPICE-like TSTAC™ eFlash model for design and test
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pp. 359-364
by
P.-D. Mauroux
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A. Virazel
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A. Bosio
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L. Dilillo
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P. Girard
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S. Pravossoudovitch
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B. Godard
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G. Festes
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L. Vachez
Statistical analysis of 6T SRAM data retention voltage under process variation
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pp. 365-370
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Elena I. Vatajelu
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Joan Figueras
Decreasing test time by scan chain reorganization
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pp. 371-374
by
Pavel Bartoš
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Zdeněk Kotásek
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Jan Dohnal
Max-Fill: A method to generate high quality delay tests
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pp. 375-380
by
X. Fan
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S.M. Reddy
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I. Pomeranz
Measurement point selection for in-operation wear-out monitoring
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pp. 381-386
by
Urban Ingelsson
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Shih-Yen Chang
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Erik Larsson
Test vector overlapping based compression tool for narrow test access mechanism
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pp. 387-392
by
Jiří Jeníček
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Martin Rozkovec
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Ondřej Novák
A 20 pJ/b (10 µW) digital receiver based on a new modulation (SAS) for retinal prosthesis application
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pp. 393-394
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F. Goodarzy
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E. Skafidas
Comparison of iddt test efficiency in covering opens in SRAMs realised in two different technologies
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pp. 395-396
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Gábor Gyepes
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Juraj Brenkuš
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Daniel Arbet
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Viera Stopjaková
Advanced fault tolerant bus for multicore system implemented in FPGA
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pp. 397-398
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Martin Straka
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Jan Kastil
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Jaroslav Novotny
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Zdenek Kotasek
Validation and optimization of TMR protections for circuits in radiation environments
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pp. 399-400
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O. Ruano
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J.A. Maestro
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P. Reviriego
Reduction of FPGA resources for regular expression matching by relation similarity
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pp. 401-402
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Vlastimil Košař
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Jan Kořenek
Low-power quadrature VCO design for medical implant communication service
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pp. 403-404
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Jeong Ki Kim
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Jihoon Jeong
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Dong Sam Ha
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Hyung-soo Lee
Current sensing methodology for completion detection in self-timed systems
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pp. 405-406
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Lukáš Nagy
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Viera Stopjaková
A wireless ECG sensor node based on Huffman data encoder
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pp. 411-412
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Uroš Pešović
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Siniša Ranđić
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Zoran Stamenković
Advanced rectifier and driver for analog VU meter
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pp. 413-414
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Martin Pospisilik
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Milan Adamek
Automatic property generation for the formal verification of bus bridges
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pp. 417-422
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Mathias Soeken
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Ulrich Kühne
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Martin Freibothe
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Görschwin Fe
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Rolf Drechsler
Probabilistic equivalence checking based on high-level decision diagrams
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pp. 423-428
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Anton Karputkin
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Raimund Ubar
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Mati Tombak
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Jaan Raik
Proof certificates and non-linear arithmetic constraints
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pp. 429-434
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S. Kupferschmid
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B. Becker
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T. Teige
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M. Fränzle
TLM protocol compliance checking at the Electronic System Level
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pp. 435-440
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Mohamed Bawadekji
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Daniel Große
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Rolf Drechsler
Error recovery technique for coarse-grained reconfigurable architectures
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pp. 441-446
by
Muhammad Moazam Azeem
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Stanislaw J. Piestrak
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Olivier Sentieys
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Sebastien Pillement
Behavior of CMOS polymorphic circuits in high temperature environment
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pp. 447-452
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Richard Ruzicka
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Vaclav Simek
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Lukas Sekanina
Dynamic placement applications into Self Adaptive network on FPGA
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pp. 453-456
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Petr Honzík
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Jiří Kadlec
Minimal physical resource allocation of pi-calculus schedules to dynamically reconfigurable platforms
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pp. 457-462
by
André Seffrin
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Sorin A. Huss
TTTC: Test Technology Technical Council
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