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2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

Sept. 19 2016 to Sept. 20 2016

Storrs, CT, USA

Table of Contents

[Copyright notice]Freely available from IEEE.pp. ii-ii
ForewordFreely available from IEEE.pp. iii-iii
by Omer Khan, Maria K. Michael, Antonio Miele, Qiaoyan Yu
Table of contentsFreely available from IEEE.pp. v-vii
Author indexFreely available from IEEE.pp. 158-159
BTI aware thermal management for reliable DVFS designsFull-text access may be available. Sign in or learn about subscription options.pp. 1-6
by Hardeep Chahal, Vasileios Tenentes, Daniele Rossi, Bashir M. Al-Hashimi
Prognosis of NBTI aging using a machine learning schemeFull-text access may be available. Sign in or learn about subscription options.pp. 7-10
by Naghmeh Karimi, Ke Huang
Experimental study and analysis of soft and permanent errors in digital camerasFull-text access may be available. Sign in or learn about subscription options.pp. 11-14
by Glenn H. Chapman, Rahul Thomas, Rohan Thomas, Israel Koren, Zahava Koren
A Highly Robust Double Node Upset Tolerant latchFull-text access may be available. Sign in or learn about subscription options.pp. 15-20
by Adam Watkins, Spyros Tragouodas
Applying efficient fault tolerance to enable the preconditioned conjugate gradient solver on approximate computing hardwareFull-text access may be available. Sign in or learn about subscription options.pp. 21-26
by Alexander Schöll, Claus Braun, Hans-Joachim Wunderlich
Construction of a soft error (SEU) hardened Latch with high critical chargeFull-text access may be available. Sign in or learn about subscription options.pp. 27-30
by Hiroki Ueno, Kazuteru Namba
Design and analysis of an approximate 2D convolverFull-text access may be available. Sign in or learn about subscription options.pp. 31-34
by Ke Chen, Fabrizio Lombardi, Jie Han
Combined on-line lifetime-energy optimization for asymmetric multicoresFull-text access may be available. Sign in or learn about subscription options.pp. 35-40
by Cristiana Bolchini, Matteo Carminati, Tulika Mitra, Thannirmalai Somu Muthukaruppan
Effects of online fault detection mechanisms on Probabilistic Timing AnalysisFull-text access may be available. Sign in or learn about subscription options.pp. 41-46
by Chao Chen, Jacopo Panerati, Giovanni Beltrame
Bounding error detection latency in safety critical systems with enhanced Execution FingerprintingFull-text access may be available. Sign in or learn about subscription options.pp. 47-52
by Mojing Liu, Brett H. Meyer
Guiding Genetic Algorithms using importance measures for reliable design of embedded systemsFull-text access may be available. Sign in or learn about subscription options.pp. 53-56
by Hananeh Aliee, Stefan Vitzethum, Michael Glaß, Jürgen Teich, Emanuele Borgonovo
Fault-tolerant scheduling of multicore mixed-criticality systems under permanent failuresFull-text access may be available. Sign in or learn about subscription options.pp. 57-62
by Zaid Al-bayati, Brett H. Meyer, Haibo Zeng
Cross-layer fault-tolerant design of real-time systemsFull-text access may be available. Sign in or learn about subscription options.pp. 63-68
by Siva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar
Fault-aware sensitivity analysis for probabilistic real-time systemsFull-text access may be available. Sign in or learn about subscription options.pp. 69-74
by Luca Santinelli, Zhishan Guo, Laurent George
Low cost resilient regular expression matching on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 75-80
by Marcos T. Leipnitz, Eduardo Nunes de Souza, Gabriel L. Nazar
In-place LUT polarity inVersion to mitigate soft errors for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 81-86
by Juexiao Su, Ju-Yueh Lee, Chang Wu, Lei He
Detecting intermittent resistive faults in digital CMOS circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 87-90
by Hassan Ebrahimi, Alireza Rohani, Hans G. Kerkhoff
Soft error vulnerability assessment of the real-time safety-related ARM Cortex-R5 CPUFull-text access may be available. Sign in or learn about subscription options.pp. 91-96
by Xabier Iturbe, Balaji Venu, Emre Ozer
Efficient utilization of hierarchical iJTAG networks for interrupts managementFull-text access may be available. Sign in or learn about subscription options.pp. 97-102
by Ahmed Ibrahim, Hans G. Kerkhoff
Error recovery through partial value similarityFull-text access may be available. Sign in or learn about subscription options.pp. 103-106
by Abdulaziz Eker, Oguz Ergin
In-field functional test programs development flow for embedded FPUsFull-text access may be available. Sign in or learn about subscription options.pp. 107-110
by R. Cantoro, D. Piumatti, P. Bernardi, S. De Luca, A. Sansonetti
Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegramsFull-text access may be available. Sign in or learn about subscription options.pp. 111-114
by Filippo Giuliani, Marco Ottavi, Gian Carlo Cardarilli, Marco Re, Luca Di Nunzio, Rocco Fazzolari, Antimo Bruno, Francesco Zuliani
CoBRA: Low cost compensation of TSV failures in 3D-NoCFull-text access may be available. Sign in or learn about subscription options.pp. 115-120
by Ronak Salamat, Masoumeh Ebrahimi, Nader Bagherzadeh, Freek Verbeek
A new approach to deadlock-free fully adaptive routing for high-performance fault-tolerant NoCsFull-text access may be available. Sign in or learn about subscription options.pp. 121-126
by Amir Charif, Nacer-Eddine Zergainoh, Michael Nicolaidis
An adaptive routing algorithm to improve lifetime reliability in NoCs architectureFull-text access may be available. Sign in or learn about subscription options.pp. 127-130
by Juman Alshraiedeh, Avinash Kodi
A novel method for SEE validation of complex SoCs using Low-Energy Proton beamsFull-text access may be available. Sign in or learn about subscription options.pp. 131-134
by Gianluca Furano, Stefano Di Mascio, Tomasz Szewczyk, Alessandra Menicucci, Luigi Campajola, Francesco Di Capua, Andrea Fabbri, Marco Ottavi
Reliable PUF design using failure patterns from time-controlled power gatingFull-text access may be available. Sign in or learn about subscription options.pp. 135-140
by Xiaolin Xu, Daniel E. Holcomb
Side channel attacks on STTRAM and low-overhead countermeasuresFull-text access may be available. Sign in or learn about subscription options.pp. 141-146
by Anirudh Iyengar, Swaroop Ghosh, Nitin Rathi, Helia Naeimi
On meta-obfuscation of physical layouts to conceal design characteristicsFull-text access may be available. Sign in or learn about subscription options.pp. 147-152
by Vinay C. Patil, Arunkumar Vijayakumar, Sandip Kundu
Can flexible, domain specific programmable logic prevent IP theft?Full-text access may be available. Sign in or learn about subscription options.pp. 153-157
by Xiaotong Cui, Kaijie Wu, Siddharth Garg, Ramesh Karri
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