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Euromicro Symposium on Digital System Design, 2004. DSD 2004.

Aug. 31 2004 to Sept. 3 2004

Rennes, France

Table of Contents

DSD 2004 Euromicro Symposium on Digital System DesignFreely available from IEEE.pp. 0_2-0_2
Proceedings of the EUROMICRO Systems on Digital System Design [title page]Freely available from IEEE.pp. 0_4-0_4
Invited Papers
Design Methodology Innovations Address Manufacturing Technology Challenges: Power and PerformanceFull-text access may be available. Sign in or learn about subscription options.pp. 52-59
by Ulf Schlichtmann
Processor and Memory Architectures (S1)
Arithmetic Coding Architecture for H.264/AVC CABAC Compression SystemFull-text access may be available. Sign in or learn about subscription options.pp. 62-69
by Roberto R. Osorio, Javier D. Bruguera
Processor and Memory Architectures (S1)
A Simple Micro-Threaded Data-Driven ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 70-77
by A. Bindal, S. Brugada, T. Ha, W. Sana, M. Singh, V. Tejaswi, D. Wyland
Synthesis (HL, LS, PS) (S6)
A Novel Signed Higher-Radix Full-Adder Algorithm and Implementation with Current-Mode Multi-Valued Logic CircuitsFull-text access may be available. Sign in or learn about subscription options.pp. 80-87
by Turgay Temel, Avni Morgul, Nizamettin Aydin
Synthesis (HL, LS, PS) (S6)
Memory Aware HLS and the Implementation of Ageing VectorsFull-text access may be available. Sign in or learn about subscription options.pp. 88-95
by Gwenol? Corre, Eric Senn, Nathalie Julien, Eric Martin
Processor and Memory Architectures (S2)
A Complete Methodology for Memory Optimization in DSP ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 98-103
by F. Marteil, N. Julien, E. Senn, E. Martin
Processor and Memory Architectures (S2)
ASSEC: An Asynchronous Self-Checking RISC-based ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 104-111
by P. D. Hyde, G. Russell
Processor and Memory Architectures (S2)
Investigating Available Instruction Level Parallelism for Stack Based Machine ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 112-120
by Huibin Shi, Chris Bailey
Processor and Memory Architectures (S2)
A Proposed Mechanism for Super-Pipelined Instruction-Issue for ILP Stack MachinesFull-text access may be available. Sign in or learn about subscription options.pp. 121-129
by Chris Bailey
Processor and Memory Architectures (S2)
Compiler-Directed Dynamic Memory Disambiguation for Loop StructuresFull-text access may be available. Sign in or learn about subscription options.pp. 130-134
by Soyeb Alli, Chris Bailey
Synthesis (HL, LS, PS) (S7)
Efficient Method of Input Variable Partitioning in Functional Decomposition Based on Evolutionary AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 136-143
by Mariusz Rawski, Henry Selvaraj, Pawel Morawiecki
Synthesis (HL, LS, PS) (S7)
Cost-Efficient Implementation of Adaptive Finite State MachinesFull-text access may be available. Sign in or learn about subscription options.pp. 144-151
by Maik Boden, Manfred Koegst, Jos? Luis Tiburcio Bad?, Steffen R?
Synthesis (HL, LS, PS) (S7)
Boolean Minimizer FC-Min: Coverage Finding ProcessFull-text access may be available. Sign in or learn about subscription options.pp. 152-159
by Petr Fiser, Hana Kub?tov?
Synthesis (HL, LS, PS) (S7)
An Effective Solution of Benchmarking Problem FSM Benchmark Generator and Its Application to Analysis of State Assignment MethodsFull-text access may be available. Sign in or learn about subscription options.pp. 160-167
by Lech J?zwiak, Dominik Gawlowski, Aleksander Slusarczyk
Synthesis (HL, LS, PS) (S7)
BDD Circuit Optimization for Path Delay Fault TestabilityFull-text access may be available. Sign in or learn about subscription options.pp. 168-172
by Goerschwin Fey, Junhao Shi, Rolf Drechsler
Applications of (Embedded) Digital Systems (S15)
A Parallel VLSI Architecture for 1-Gb/s, 2048-b, Rate-1/2 Turbo Gallager Code DecoderFull-text access may be available. Sign in or learn about subscription options.pp. 174-181
by P. Ciao, G. Colavolpe, L. Fanucci
Applications of (Embedded) Digital Systems (S15)
VLSI Design of a Digital RFI Cancellation Scheme for VDSL TransceiversFull-text access may be available. Sign in or learn about subscription options.pp. 182-189
by L. Fanucci, R. Locatelli, E. Petri
Applications of (Embedded) Digital Systems (S15)
Shift Invert Coding (SINV) for Low Power VLSIFull-text access may be available. Sign in or learn about subscription options.pp. 190-194
by Jayapreetha Natesan, Damu Radhakrishnan
Applications of (Embedded) Digital Systems (S15)
Generalized Analytical Model for the Design of Irregularly Shaped Power Planes and Passives in Mixed Signal ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 195-199
by Jeffrey McFiggins, Marie Yvanoff, Jayanti Venkataraman
Applications of (Embedded) Digital Systems (S15)
IP-Block Based Integration of Very High Performance WLAN ModemFull-text access may be available. Sign in or learn about subscription options.pp. 200-207
by Jussi Roivainen, Jukka Rautio
DSP + MISC (S17)
{\text{\{ 2}}^{\text{n}} + 1,2^{n + k} ,2^n - 1\} : A New RNS Moduli Set ExtensionFull-text access may be available. Sign in or learn about subscription options.pp. 210-217
by Ricardo Chaves, Leonel Sousa
DSP + MISC (S17)
Image Processing Algorithms on Reconfigurable Architecture using HandelCFull-text access may be available. Sign in or learn about subscription options.pp. 218-226
by V. Muthukumar, Daggu Venkateshwar Rao
DSP + MISC (S17)
Analysis and Hardware Design of a Scalable Dual JPEG-2000 Entropy CoderFull-text access may be available. Sign in or learn about subscription options.pp. 227-233
by I. Aouadi, O. Hammami
DSP + MISC (S17)
On the Packet-Switched Implementation of a Discrete-Time CNNFull-text access may be available. Sign in or learn about subscription options.pp. 234-241
by Suleyman Malki, Lambert Spaanenburg
Special Architectures (S5)
Partially Reconfigurable Matrix Multiplication for Area and Time Efficiency on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 244-248
by Luo Jianwen, Jong Ching Chuen
Special Architectures (S5)
Design and Implementation of Reciprocal Unit Using Table Look-up and Newton-Raphson IterationFull-text access may be available. Sign in or learn about subscription options.pp. 249-253
by Umut K???kkabak, Ahmet Akkas
Special Architectures (S5)
Finite Precision Analysis of Support Vector Machine Classification in Logarithmic Number SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 254-261
by Faisal M. Khan, Mark G. Arnold, William M. Pottenger
Special Architectures (S5)
Evaluation of SIMD Architecture Enhancement in Embedded Processors for MPEG-4Full-text access may be available. Sign in or learn about subscription options.pp. 262-269
by Ali R. Iranpour, Krzysztof Kuchcinski
Processor and Memory Architectures (S3)
Memory Requirement Optimization with Loop Fusion and Loop ShiftingFull-text access may be available. Sign in or learn about subscription options.pp. 272-278
by Qubo Hu, Martin Palkovic, Per Gunnar Kjeldsberg
Processor and Memory Architectures (S3)
Multi-log Processor - Towards Scalable Event-Driven MultiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 279-286
by Vinod Viswanath
Synthesis (S9)
Information Trans-Coders in Information-Driven Circuit SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 288-397
by L. J?zwiak, S. Bieganski
Synthesis (S9)
Towards Behavioral Synthesis of Asynchronous Circuits - An Implementation Template Targeting Syntax Directed Compilation.Full-text access may be available. Sign in or learn about subscription options.pp. 298-305
by S. F. Nielsen, J. Spars?, J. Madsen
SOC (S13)
A Constraints Programming Approach to Communication Scheduling on SoPC ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 308-315
by Christophe Wolinski, Krzysztof Kuchcinski, Maya Gokhale
SOC (S13)
Easy SoC Design with VCI SystemC AdaptersFull-text access may be available. Sign in or learn about subscription options.pp. 316-323
by Salim Ouadjaout, Dominique Houzet
Special Architectures (S4)
Multi-Pipeline Implementations of Real-Time Vector DFTFull-text access may be available. Sign in or learn about subscription options.pp. 326-333
by Alexander A. Petrovsky, Sergei L. Shkredov
Special Architectures (S4)
Scalable and Area Efficient Concurrent Interleaver for High Throughput Turbo-DecodersFull-text access may be available. Sign in or learn about subscription options.pp. 334-341
by Filippo Speziali, Julien Zory
Special Architectures (S4)
Pipeline-Level Control of Self-Resetting PipelinesFull-text access may be available. Sign in or learn about subscription options.pp. 342-349
by Abdel Ejnioui, Abdelhalim Alsharqawi
Special Architectures (S4)
An Energy-Efficient Adaptive Multiple-Issue ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 350-357
by Mars Lan, Morteza Biglari-Abhari
Special Architectures (S4)
A High Speed FPGA Implementation of the Rijndael AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 358-362
by Refik Sever, A. Neslin Ismailglu, Yusuf ?. Tekmen, Murat Askar, Burak Okcan
Special Architectures (S4)
Mixed Synchronous/Asynchronous State Memory for Low Power FSM DesignFull-text access may be available. Sign in or learn about subscription options.pp. 363-370
by Cao Cao, Bengt Oelmann
Specification and Modeling (S10)
A Formal Verification Methodology for IP-based DesignsFull-text access may be available. Sign in or learn about subscription options.pp. 372-379
by Daniel Karlsson, Petru Eles, Zebo Peng
Specification and Modeling (S10)
Diminished-1 Modulo 2^n + 1 Squarer DesignFull-text access may be available. Sign in or learn about subscription options.pp. 380-386
by H. T. Vergos, C. Efstathiou
Specification and Modeling (S10)
Handel-C implementation of Classical Component Labelling AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 387-393
by Miroslaw Jablonski, Marek Gorgon
Specification and Modeling (S10)
Power Consumption Characterization and Modeling of Embedded Memories in XILINX VIRTEX 400E FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 394-401
by David Ell?ouet, Nathalie Julien, Dominique Houzet, J.-G. Cousin, Eric Martin
Specification and Modeling (S10)
Mapping of High-Level SDL Models to Efficient Implementations for TinyOSFull-text access may be available. Sign in or learn about subscription options.pp. 402-406
by Daniel Dietterle, Jerzy Ryman, Kai Dombrowski, Rolf Kraemer
Validation / Verification (S12)
A Heuristic for Wiring-Aware Built-In Self-Test SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 408-415
by Abdil Rashid Mohamed, Zebo Peng, Petru Eles
Validation / Verification (S12)
The Logarithmic Checking Method for On-Line Testing of Computing Circuits for Processing of the Approximated DataFull-text access may be available. Sign in or learn about subscription options.pp. 416-423
by A. Drozd, R. Al-Azzeh, J. Drozd, M. Lobachev
Validation / Verification (S12)
Scene Management Models and Overlap Tests for Tile-Based RenderingFull-text access may be available. Sign in or learn about subscription options.pp. 424-431
by I. Antochi, B. Juurlink, S. Vassiliadis, P. Liuha
Validation / Verification (S12)
Evaluation of Transient Fault Susceptibility in Microprocessor SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 432-439
by P. Gawkowski, J. Sosnowski
Validation / Verification (S12)
Topological BDP fault simulation methodFull-text access may be available. Sign in or learn about subscription options.pp. 440-443
by V. Hahanov, I. Hahanova, S. Hyduke
Validation / Verification (S12)
Techniques for Formal Verification of Digital Systems: A System ApproachFull-text access may be available. Sign in or learn about subscription options.pp. 444-449
by Hamid Shojaei, Habib Ghayoumi
Applications of (Embedded) Digital Systems (S16)
Efficient Rapid Prototyping of Image and Video Processing AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 452-458
by S. Vitabile, A. Gentile, S. M. Siniscalchi, F. Sorbello
Applications of (Embedded) Digital Systems (S16)
A Distributed Arithmetic Online Rotator for Signal Processing ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 459-466
by Robert Prain, Andrew Paplinski
Applications of (Embedded) Digital Systems (S16)
FPGA Based Design of the Railway's Interlocking EquipmentsFull-text access may be available. Sign in or learn about subscription options.pp. 467-473
by Radek Dobias, Hana Kubatova
Specification and Modeling (S11)
CASSE: A System-Level Modeling and Design-Space Exploration Tool for Multiprocessor Systems-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 476-483
by V?ctor Reyes, Tom?s Bautista, Gustavo Marrero, Pedro P. Carballo, Wido Kruijtzer
Specification and Modeling (S11)
Modeling a Network Processor Using Object Oriented TechniquesFull-text access may be available. Sign in or learn about subscription options.pp. 484-490
by Liam Noonan, Colin Flanagan
SOC (S14)
An Energy-Efficient Network-on-Chip for a Heterogeneous Tiled Reconfigurable Systems-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 492-498
by Nikolay Kavaldjiev, Gerard J. M. Smit
SOC (S14)
Interesting Applications of Atmel AVR MicrocontrollersFull-text access may be available. Sign in or learn about subscription options.pp. 499-506
by Stanislav Korbel, Vlastimil Janes
Special Architectures (S5)
A Fast and Well-Structured MultiplierFull-text access may be available. Sign in or learn about subscription options.pp. 508-515
by Jung-Yup Kang, Jean-Luc Gaudiot
Special Architectures (S5)
Fast Reconfigurable Hardware for the M-ary Modular ExponentiationFull-text access may be available. Sign in or learn about subscription options.pp. 516-523
by Luiza de Macedo Mourelle, Nadia Nedjah
Special Architectures (S5)
Towards New Real-Time Processor: The Multioperand MSB-First Real-Time AdderFull-text access may be available. Sign in or learn about subscription options.pp. 524-529
by Kuspriyanto, Yusrila Y. Kerlooza
MISC + Algorithm (S18)
Workload Simulation Method for Evaluation of Application Feasibility in a Mobile Multiprocessor PlatformFull-text access may be available. Sign in or learn about subscription options.pp. 532-539
by Jari Kreku, Jani Penttil?, Janne Kangas, Juha-Pekka Soininen
MISC + Algorithm (S18)
An Automated Methodology for Low Electro-Magnetic Emissions Digital Circuits DesignFull-text access may be available. Sign in or learn about subscription options.pp. 540-547
by Ivan Blunno, Guy Alain Narboni, Claudio Passerone
MISC + Algorithm (S18)
An Efficient Exponential Algorithm with Exponential Convergence RateFull-text access may be available. Sign in or learn about subscription options.pp. 548-555
by Chichyang Chen, Kuo-Sheng Cheng
MISC + Algorithm (S18)
What to Adapt in a High-Performance MicroprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 556-563
by Pedro Trancoso
Sensor Networks (S19)
DCP: A New Data Collection Protocol for Bluetooth-Based Sensor NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 566-573
by Matthias Handy, Frank Grassert, Dirk Timmermann
Sensor Networks (S19)
Hybrid Greedy/Face Routing for Ad-Hoc Sensor NetworkFull-text access may be available. Sign in or learn about subscription options.pp. 574-578
by J. Li, L. Gewali, H. Selvaraj, V. Muthukumar
Sensor Networks (S19)
Architecture of Wireless Sensor Node using Novel Ultra-Wideband Modulation SchemeFull-text access may be available. Sign in or learn about subscription options.pp. 579-586
by Matthew D'Souza, Adam Postula
Sensor Networks (S19)
Phased Array and Adaptive Antenna Transceivers in Wireless Sensor NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 587-592
by Ruimin Huang, Yiannos Manoli
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