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Euro ASIC '91

May 27 1991 to May 31 1991

Paris, France

Table of Contents

UDL/I standardization effort another approach to HDL standardFull-text access may be available. Sign in or learn about subscription options.pp. 388,389,390,391,392,393
by O. Karatsu
A good input ordering for circuit verification based on binary decision diagramsFull-text access may be available. Sign in or learn about subscription options.pp. 385,386,387
by G. Saucier, F. Poirot
Application example of multi-level digital design verification by the SFG-tracing methodologyFull-text access may be available. Sign in or learn about subscription options.pp. 379,380,381,382,383,384
by L. Claesen, M. Genoe, E. Verlind, F. Proesmans, H. De Man
Datapath layout generation with in-the-cell routing and optimal column resequencingFull-text access may be available. Sign in or learn about subscription options.pp. 373,374,375,376
by P.J. Drenth, C. Strolenberg
G2L: system for converting low-level geometrical designs to a higher level representationFull-text access may be available. Sign in or learn about subscription options.pp. 366,367,368,369,370,371
by E. Pajarre, T. Ritoniemi, H. Tenhunen
Evaluation of VLSI layout style implementations for efficiencyFull-text access may be available. Sign in or learn about subscription options.pp. 362,363,364,365
by M. Robert, J. Trauchessec, G. Cathebras, V. Bonzom, N. Azemard, D. Deschacht, D. Auvergne
Using a CMOS ASIC technology for the development of an integrated ISFET sensorFull-text access may be available. Sign in or learn about subscription options.pp. 356,357,358,359
by K. Dzahini, F. Gaffiot, M. Le Helley
An A/D-chip for accurate power measurementFull-text access may be available. Sign in or learn about subscription options.pp. 352,353,354,355
by R. Rauscher, V. Grupe
ASIC design considerations for power management in laptop computersFull-text access may be available. Sign in or learn about subscription options.pp. 348,349,350,351
by Y.A. Dubois, J.J. Farrell
Design of a robust analog/digital ASIC interface for hard industrial environmentFull-text access may be available. Sign in or learn about subscription options.pp. 344,345,346,347
by J. Suutari, H. Tenhunen, J. Nikula
Digital speed regulation for a washing machine motorFull-text access may be available. Sign in or learn about subscription options.pp. 340,341,342,343
by C. Ferrer, J.M. Aguirre
A temperature and voltage measurement cell for VLSI circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 334,335,336,337,338
by G.M. Quenot, N. Paris, B. Zavidovique
Testing ASICs at-speedFull-text access may be available. Sign in or learn about subscription options.pp. 328,329,330,331,332
by C. Gauthron
Integrating verification testing and logic synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 322,323,324,325,326
by W. Murzyn, A. Krasniewski
Design of highly reliable VLSI processors incorporating concurrent error detection/correctionFull-text access may be available. Sign in or learn about subscription options.pp. 316,317,318,319,320,321
by G. Russell, I.D. Elliott
High-quality physical designs of CMOS ICsFull-text access may be available. Sign in or learn about subscription options.pp. 310,311,312,313,314,315
by J.J.T. Sousa, F.M. Goncalves, J.P. Teixeira
High speed CMOS operational amplifierFull-text access may be available. Sign in or learn about subscription options.pp. 305,306,307,308
by S. Schwehr, T. Fuchs, K. Dzahini, B. Boutherin, M. Le Helley
6 bits programmable VHF amplifierFull-text access may be available. Sign in or learn about subscription options.pp. 301,302,303,304
by C. Vanhecke
ASIC chip set development for PCM 2 and 3-ary group MUX and DEMUX with EIS projectFull-text access may be available. Sign in or learn about subscription options.pp. 297,298,299,300
by Liang Jie
ASIC cryptographical processor based on DESFull-text access may be available. Sign in or learn about subscription options.pp. 292,293,294,295
by I. Verbauwhede, F. Hoornaert, J. Vandewalle, H. De Man
Test generation of controllers using the synthesis specificationsFull-text access may be available. Sign in or learn about subscription options.pp. 284,285,286,287,288,289
by M. Karam, G. Saucier, C. Jay
Comprehensive CAD support for boundary scan implementation in ASICsFull-text access may be available. Sign in or learn about subscription options.pp. 278,279,280,281,282,283
by P. Lestrat, R. Leveugle, P. Magarshack
Test generation using cross-observability calculationsFull-text access may be available. Sign in or learn about subscription options.pp. 272,273,274,275,276,277
by E. Cerny, E.M. Aboulhamid, C. Mauras, P. Rioux
On the construction of very large integer multipliersFull-text access may be available. Sign in or learn about subscription options.pp. 266,267,268,269
by G. Hotz, P. Molitor, W. Zimmer
A fast data path multiplierFull-text access may be available. Sign in or learn about subscription options.pp. 260,261,262,263,264,265
by C. Priol, P. Magarshack
Real time image processing system: design of an area CCD sensor driving integrated circuitFull-text access may be available. Sign in or learn about subscription options.pp. 254,255,256,257
by E. Fauvet, M. Paindavoine, J.-F. Kirilenko, M. Robert, D. Deschacht, D. Auvergne
An ASIC for image dilation and erosionFull-text access may be available. Sign in or learn about subscription options.pp. 251,252,253
by M. Baatour, J. Rampon, Y. Tertre
A digital CMOS fully connected neural network with in-circuit learning capability and automatic identification of spurious attractorsFull-text access may be available. Sign in or learn about subscription options.pp. 247,248,249,250
by J.-D. Gascuel, M. Weinfeld, S. Chakroun
Serial data interface for telecommunication satellitesFull-text access may be available. Sign in or learn about subscription options.pp. 243,244,245,246
by J. Vanneuville, H. Manhaeve, D. Gevaert
Design of a complex combinational ASIC with educational aimsFull-text access may be available. Sign in or learn about subscription options.pp. 239,240,241,242
by P. Amblard, M. Hollett, S. Audie, E. Bittar, C. Chaudy, P. Coulomb, S. Le Men, O. Ondoa, E. Piot, F. Pogodalla
Implementation of a linear array element for matrix multiplicationFull-text access may be available. Sign in or learn about subscription options.pp. 236,237,238
by M.A. Morante, L. Saiz de Quevedo, P. Tabuenca, J.I. Martinez, E. Villar
Optimal module orientation by block rotation and wire length minimisationFull-text access may be available. Sign in or learn about subscription options.pp. 230,231,232,233,234
by P.J. Drenth, J.G.G.P. van Gisbergen, M. Lousberg
A new graph theoretical approach to the selection of rip-upsFull-text access may be available. Sign in or learn about subscription options.pp. 224,225,226,227,228,229
by M. Bartholomeus, M. Raith
A genetic algorithm for the routing of VLSI circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 218,219,220,221,222,223
by M. Geraci, P. Orlando, F. Sorbello, G. Vassallo
Timing driven pin assignment in a hierarchical design environmentFull-text access may be available. Sign in or learn about subscription options.pp. 212,213,214,215,216,217
by G. Meixner, G. Zimmermann
ACC: automatic cell characterizationFull-text access may be available. Sign in or learn about subscription options.pp. 204,205,206,207,208,209
by K. Anshumali
Power calculation for high density CMOS gate arraysFull-text access may be available. Sign in or learn about subscription options.pp. 198,199,200,201,202,203
by W. Eisenmann, M. Kohl
High precision SPICE models for the simulation of analogue CMOS circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 192,193,194,195,196,197
by B. Ankele, F. Schrank
A new method for the minimization of memory area in high level synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 184,185,186,187,188,189
by B. Rouzeyre, G. Sagnes
Flexible datapath compilation for PhideoFull-text access may be available. Sign in or learn about subscription options.pp. 178,179,180,181,182,183
by A. van der Werf, B.T. McSweeney, J.L. van Meerbergen, P.E.R. Lippens, W.F.J. Verhaegh
Resource assignment with different target architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 172,173,174,175,176,177
by A. Mignotte, M. Crastes de Paulet
Searching processorFull-text access may be available. Sign in or learn about subscription options.pp. 167,168,169,170
by J.B. Barbosa, M.B. Calha, I.C. Teixeira
Pipeline based design for numerically controlled oscillatorFull-text access may be available. Sign in or learn about subscription options.pp. 162,163,164,165
by Ji Lijiu, Li Dina, Liang Qinglin, Sheng Shimin
VLSI design of an 8-bit fixed point CORDIC processor with extended operation setFull-text access may be available. Sign in or learn about subscription options.pp. 158,159,160,161
by D.E. Metafas, G.A. Krikis, C.E. Goutis
VLSI chip set for floating point vector processingFull-text access may be available. Sign in or learn about subscription options.pp. 154,155,156,157
by A. Laudenbach, M. Glesner, P. Windirsch, J. Plahl, W. Clemens
Algebraic decomposition of MCNC benchmark FSMs for logic synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 146,147,148,149,150,151
by T. Muller-Wipperfurth, M. Geiger
Automatic synthesis of Boolean functions on Xilinx and Actel programmable devicesFull-text access may be available. Sign in or learn about subscription options.pp. 142,143,144,145,146
by P. Sicard, M. Crastes, K. Sakouti, G. Saucier
An efficient program for logic synthesis of mod-2 sum expressionsFull-text access may be available. Sign in or learn about subscription options.pp. 136,137,138,139,140,141
by P.W. Besslich, M.W. Riege
VLSI ASIC design for MAC video processing integration in SGS-Thomson microelectronics chip setFull-text access may be available. Sign in or learn about subscription options.pp. 131,132,133,134
by A. Lorenzi, V. Verfaillie, G. Vanneuville, N. Chaumartin, G. Gerot, J.M. Troude
A double-sourced ASIC for contactless badgesFull-text access may be available. Sign in or learn about subscription options.pp. 128,129,130
by R. Petigny, P. Cabon
A mixed-mode ASIC for interface control of smart-card parcmeterFull-text access may be available. Sign in or learn about subscription options.pp. 124,125,126,127
by E. Compagne, F. Ilie
VLSI-oriented asynchronous controller synthesis based on a flip-flop cell array structureFull-text access may be available. Sign in or learn about subscription options.pp. 117,118,119,120,121,122
by K.R. Cho, M. Ikeda, K. Asada
Synthesis and partitioning of standard cells for floorplan optimizationFull-text access may be available. Sign in or learn about subscription options.pp. 112,113,114,115,116
by E. Chotin, T. Besson, G. Saucier
A new approach to timing driven partitioning of combinational logicFull-text access may be available. Sign in or learn about subscription options.pp. 106,107,108,109,110,111
by N. Wehn, M. Glesner
CMOS video camerasFull-text access may be available. Sign in or learn about subscription options.pp. 100,101,102,103
by G. Wang, D. Renshaw, P.B. Denyer, M. Lu
A dedicated circuit for real time motion estimationFull-text access may be available. Sign in or learn about subscription options.pp. 96,97,98,99
by O. Colavin, A. Artieri, J.-F. Naviner, R. Pacalet
A data-flow processor for real-time low-level image processingFull-text access may be available. Sign in or learn about subscription options.pp. 92,93,94,95
by G. Quenot, B. Zavidovique
An image decoding ASIC for space-based applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 86,87,88,89,90,91
by D.B. Kasle, G. DeMicheli
VHDL in logic synthesis-an applications perspectiveFull-text access may be available. Sign in or learn about subscription options.pp. 78,79,80,81,82
by W. Ries, K.M. Just
Reduced voltage swing, high speed CMOS driver, receiver techniques for multiple chip set applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 74,75,76
by P.D. Ta
SICURE-a crypto chip for rapid enciphermentFull-text access may be available. Sign in or learn about subscription options.pp. 68,69,70,71,72,73
by H.M. Deppermann, J. Gessner, S. Kosters, S. Wallstab
Design and implementation of a dedicated neural network for handwritten digit recognitionFull-text access may be available. Sign in or learn about subscription options.pp. 63,64,65,66,67
by P.-Y. Alla, L. Masse-Navette, J. Ouali, G. Saucier, S. Knerr, L. Personnaz, G. Dreyfus
Processor chip design on submicron ASICsFull-text access may be available. Sign in or learn about subscription options.pp. 58,59,60,61,62
by H. Schettler
A 16/24-bit DSP-ASIC coprocessor for AC motor modellingFull-text access may be available. Sign in or learn about subscription options.pp. 53,54,55,56
by S.J. Ovaska, O. Vainio, J. Pasanen
Single-chip RNS two port parallel adaptor for wave digital filtersFull-text access may be available. Sign in or learn about subscription options.pp. 49,50,51,52
by G.C. Cardarilli, F. Sargeni
VLSI implementation of a cochlear modelFull-text access may be available. Sign in or learn about subscription options.pp. 45,46,47,48
by N. Avellana, F. Garrido, J. Carrabina, E. Valderrama, P. Gomez
A SIMD machine for beamforming on a chipFull-text access may be available. Sign in or learn about subscription options.pp. 41-44
by J.-P. Giacalone, Y. Del Gallo
KISS-16: realization of a DSP optimized for digital mobile radio systemsFull-text access may be available. Sign in or learn about subscription options.pp. 36,37,38,39,40
by H. Sahm, J. Schuck, H. Ebert, D. Weinsziehr, J. Preissner, G. Mahlich
Algorithmic ADC for use in ASIC designFull-text access may be available. Sign in or learn about subscription options.pp. 29,30,31,32,33
by K. Deevy
A smart power IC for high side driver applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 25,26,27,28
by Y. Droinet
DSP-ASIC based voltage feedback switching regulator chip for electromechanical contactorFull-text access may be available. Sign in or learn about subscription options.pp. 20,21,22,23,24
by P. Solanti, T. Karema, H. Tenhunen
A versatile building-block for high-speed current-mode analog ICsFull-text access may be available. Sign in or learn about subscription options.pp. 14,15,16,17,18,19
by R.B. Steck, A. Kostka, K. Lehmann
DBIMOS: the mix in one approachFull-text access may be available. Sign in or learn about subscription options.pp. 8,9,10,11,12
by E. Teck
Advances in high speed ECL technology and interconnection techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 2,3,4,5,6,7
by K.-I. Ohno
Euro ASIC '91 (Cat. No.91TH0367-3)Freely available from IEEE.pp. 0_1-0_1
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