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IEEE East-West Design & Test Symposium (EWDTS 2008)

Oct. 9 2008 to Oct. 12 2008

Lviv

Table of Contents

[Title page]Freely available from IEEE.pp. 1-1
[Copyright notice]Freely available from IEEE.pp. 1-1
Testing the control part of peripheral interfacesFull-text access may be available. Sign in or learn about subscription options.pp. 55-58
by S. Zielski, J. Sosnowski
Concurrent processes synchronisation in statecharts for FPGA implementationFull-text access may be available. Sign in or learn about subscription options.pp. 59-64
by Grzegorz Łabiak, Marian Adamski
Characterization of CMOS sequential standard cells for defect based voltage testingFull-text access may be available. Sign in or learn about subscription options.pp. 49-54
by A. Wielgus, W. A. Pleskacz
An advanced method for synthesizing TLM2-based interfacesFull-text access may be available. Sign in or learn about subscription options.pp. 104-108
by Nadereh Hatami, Zainalabedin Navabi
Coverage-directed verification of microprocessor units based on cycle-accurate contract specificationsFull-text access may be available. Sign in or learn about subscription options.pp. 84-87
by Alexander Kamkin
Multidimensional loop fusion for low-powerFull-text access may be available. Sign in or learn about subscription options.pp. 92-95
by Dmytro Lazorenko
On macroplaces in Petri netsFull-text access may be available. Sign in or learn about subscription options.pp. 418-422
by Andrei Karatkevich
A novel timing-driven placement algorithm using smooth timing analysisFull-text access may be available. Sign in or learn about subscription options.pp. 137-140
by Andrey Ayupov, Leonid Kraginskiy
RTL-TLM equivalence checking based on simulationFull-text access may be available. Sign in or learn about subscription options.pp. 214-217
by Nicola Bombieri, Franco Fummi, Graziano Pravadelli
An optimized CLP-based technique for generating propagation sequencesFull-text access may be available. Sign in or learn about subscription options.pp. 25-29
by F. Fummi, V. Guarnieri, C. Marconcini, G. Pravadelli
Digital lock detector for PLLFull-text access may be available. Sign in or learn about subscription options.pp. 141-142
by Vazgen Melikyan, Aristakes Hovsepyan, Mkrtich Ishkhanyan, Tigran Hakobyan
Partitioning, floor planning, detailed placement and routing techniques for schematic generation of analog netlistFull-text access may be available. Sign in or learn about subscription options.pp. 379-382
by Bikram Garg, Ashish Agrawal, Rajeev Sehgal, Amarpal Singh, Manish Khanna
Test suite consistency verificationFull-text access may be available. Sign in or learn about subscription options.pp. 235-239
by Sergiy Boroday, Alexandre Petrenko, Andreas Ulrich
Testability analysis method for hardware and software based on assertion librariesFull-text access may be available. Sign in or learn about subscription options.pp. 163-167
by Maryna Kaminska, Roman Prikhodchenko, Artem Kubirya, Pavel Mocar
Utilizing HDL simulation engines for accelerating design and test processesFull-text access may be available. Sign in or learn about subscription options.pp. 371-375
by Najmeh Farajipour, S. Behdad Hosseini, Zainalabedin Navabi
Diagnosis of SoC faulty memory cells for embedded repairFull-text access may be available. Sign in or learn about subscription options.pp. 143-148
by Vladimir Hahanov, Eugenia Litvinova, Karina Krasnoyaruzhskaya, Sergey Galagan
An IEEE 1500 compatible wrapper architecture for testing cores at transaction levelFull-text access may be available. Sign in or learn about subscription options.pp. 178-181
by Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi
Reliable NoC architecture utilizing a robust rerouting algorithmFull-text access may be available. Sign in or learn about subscription options.pp. 200-203
by Armin Alaghi, Mahshid Sedghi, Naghmeh Karimi, Mahmood Fathy, Zainalabedin Navabi
Automating Hardware/Software partitioning using dependency GraphFull-text access may be available. Sign in or learn about subscription options.pp. 196-199
by Somayeh Malekshahi, Mahshid Sedghi, Zainalabedin Navabi
System level hardware design and simulation with SystemAdaFull-text access may be available. Sign in or learn about subscription options.pp. 190-193
by Negin Mahani, Parnian Mokri, Zainalabedin Navabi
HotSpot : Visualizing dynamic power consumption in RTL designsFull-text access may be available. Sign in or learn about subscription options.pp. 45-48
by T. English, K.L. Man, E. Popovici, M.P. Schellekens
Performance evaluation of In-Circuit Testing on QCA based circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 375-378
by Nasim Kazemi-fard, Maryam Ebrahimpour, Mostafa Rahimi, Mohammad Tehrani, Keivan Navi
SoC software components diagnosis technologyFull-text access may be available. Sign in or learn about subscription options.pp. 155-158
by Svetlana Chumachenko, Wajeb Gharibi, Anna Hahanova, Aleksey Sushanov
Vector-logical diagnosis method for SOC functionalitiesFull-text access may be available. Sign in or learn about subscription options.pp. 159-162
by Vladimir Hahanov, Olesya Guz, Natalya Kulbakova, Maxim Davydov
Parity prediction method for on-line testing of a Barrel-shifterFull-text access may be available. Sign in or learn about subscription options.pp. 208-215
by A. Drozd, S. Antoshchuk, A. Rucinski, A. Martinuk
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