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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on

Apr. 16 1997 to Apr. 18 1997

Napa Valley, CA

ISSN: 1082-3409

ISBN: 0-8186-8159-4

Table of Contents

Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186)Freely available from IEEE.pp. iii-iii
IntroductionFreely available from IEEE.pp. ix
Program CommitteeFreely available from IEEE.pp. x
Session 1: Device Architecture
An FPGA architecture for DRAM-based systolic computationsFull-text access may be available. Sign in or learn about subscription options.pp. 2
by N. Margolus
Session 1: Device Architecture
Garp: a MIPS processor with a reconfigurable coprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 12
by J.R. Hauser, J. Wawrzynek
Session 1: Device Architecture
A time-multiplexed FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 22
by S. Trimberger, D. Carberry, A. Johnson, J. Wong
Session 2: Communication Applications
An FPGA-based coprocessor for ATM firewallsFull-text access may be available. Sign in or learn about subscription options.pp. 30
by J.T. McHenry, P.W. Dowd, F.A. Pellegrino, T.M. Carrozzi, W.B. Cocks
Session 2: Communication Applications
A wireless LAN demodulator in a Pamette: design and experienceFull-text access may be available. Sign in or learn about subscription options.pp. 40
by T. McDermott, P. Ryan, M. Shand, D. Skellern, T. Percival, N. Weste
Session 3: Run Time Reconfiguration
Incremental reconfiguration for pipelined applicationsFull-text access may be available. Sign in or learn about subscription options.pp. 47
by H. Schmit
Session 3: Run Time Reconfiguration
Compilation tools for run-time reconfigurable designsFull-text access may be available. Sign in or learn about subscription options.pp. 56
by W. Luk, N. Shirazi, P.Y.K. Cheung
Session 3: Run Time Reconfiguration
A dynamic reconfiguration run-time systemFull-text access may be available. Sign in or learn about subscription options.pp. 66
by J. Burns, A. Donlin, J. Hogg, S. Singh, M. De Wit
Session 4: Architectures for Run Time Reconfiguration
The swappable logic unit: a paradigm for virtual hardwareFull-text access may be available. Sign in or learn about subscription options.pp. 77
by G. Brebner
Session 4: Architectures for Run Time Reconfiguration
The Chimaera reconfigurable functional unitFull-text access may be available. Sign in or learn about subscription options.pp. 87
by S. Hauck, T.W. Fry, M.M. Hosler, J.P. Kao
Session 5: Architecture
Computing kernels implemented with a wormhole RTR CCMFull-text access may be available. Sign in or learn about subscription options.pp. 98
by R.A. Bittner, Jr., P.M. Athanas
Session 5: Architecture
Mapping applications to the RaPiD configurable architectureFull-text access may be available. Sign in or learn about subscription options.pp. 106
by C. Ebeling, D.C. Cronquist, P. Franklin, J. Secosky, S.G. Berg
Session 5: Architecture
Defect tolerance on the Teramac custom computerFull-text access may be available. Sign in or learn about subscription options.pp. 116
by W.B. Culbertson, R. Amerson, R.J. Carter, P. Kuekes, G. Snider
Session 6: Performance
Systems performance measurement on PCI PametteFull-text access may be available. Sign in or learn about subscription options.pp. 125
by L. Moll, M. Shand
Session 6: Performance
The RAW benchmark suite: computation structures for general purpose computingFull-text access may be available. Sign in or learn about subscription options.pp. 134
by J. Babb, M. Frank, V. Lee, E. Waingold, R. Barua, M. Taylor, J. Kim, S. Devabhaktuni, A. Agarwal
Session 7: Software Tools
Automated field-programmable compute accelerator design using partial evaluationFull-text access may be available. Sign in or learn about subscription options.pp. 145
by Qiang Wang, D.M. Lewis
Session 7: Software Tools
FPGA synthesis on the XC6200 using IRIS and Trianus/Hades (or from heaven to hell and back again)Full-text access may be available. Sign in or learn about subscription options.pp. 155
by R. Woods, S. Ludwig, J. Heron, D. Trainor, S. Gehring
Session 7: Software Tools
High level compilation for fine grained FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 165
by M. Gokhale, D. Gomersall
Session 8: CAD Applications
Acceleration of an FPGA routerFull-text access may be available. Sign in or learn about subscription options.pp. 175
by P.K. Chan, M.D.F. Schlag
Session 8: CAD Applications
Fault simulation on reconfigurable hardwareFull-text access may be available. Sign in or learn about subscription options.pp. 182
by M. Abramovici, P. Menon
Session 9: Image Processing Applications
Automated target recognition on SPLASH 2Full-text access may be available. Sign in or learn about subscription options.pp. 192
by M. Rencher, B.L. Hutchings
Session 9: Image Processing Applications
Real-time stereo vision on the PARTS reconfigurable computerFull-text access may be available. Sign in or learn about subscription options.pp. 201
by J. Woodfill, B. Von Herzen
Session 9: Image Processing Applications
Increased FPGA capacity enables scalable, flexible CCMs: an example from image processingFull-text access may be available. Sign in or learn about subscription options.pp. 211
by J. Greenbaum, M. Baxter
Session 10: Arithmetic Applications
Comparison of arithmetic architectures for Reed-Solomon decoders in reconfigurable hardwareFull-text access may be available. Sign in or learn about subscription options.pp. 219
by C. Paar, M. Rosner
Session 10: Arithmetic Applications
Implementation of single precision floating point square root on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 226
by Yamin Li, Wanming Chu
Poster Papers
Datapath-oriented FPGA mapping and placement for configurable computingFull-text access may be available. Sign in or learn about subscription options.pp. 234
by T.J. Callahan, J. Wawrzynek
Poster Papers
Mapping a real-time video algorithm to a context-switched FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 236
by S. Kelem
Poster Papers
A parallel hardware evolvable computer POLYPFull-text access may be available. Sign in or learn about subscription options.pp. 238
by U. Tangen, L. Schulte, J.S. McCaskill
Poster Papers
Laser defect correction applications to FPGA based custom computersFull-text access may be available. Sign in or learn about subscription options.pp. 240
by G.H. Chapman, B. Dufort
Poster Papers
Speech recognition HMM training on reconfigurable parallel processorFull-text access may be available. Sign in or learn about subscription options.pp. 242
by Hyun-Kyu Yun, A. Smith, H. Silverman
Poster Papers
Efficient implementation of the DCT on custom computersFull-text access may be available. Sign in or learn about subscription options.pp. 244
by N.W. Bergmann, Y.Y. Chung, B.K. Gunther
Poster Papers
On acceleration of the check tautology logic synthesis algorithm using an FPGA-based reconfigurable coprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 246
by J. Cong, J. Peck
Poster Papers
Index of AuthorsFreely available from IEEE.pp. 249
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