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2006 14th Annual IEEE Symposium on Field Programmable Custom Computing Machines

April 24 2006 to April 26 2006

Napa, CA

Table of Contents

Session 1: Supercomputer Applications
A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable SupercomputerFull-text access may be available. Sign in or learn about subscription options.pp. 3-12
Session 1: Supercomputer Applications
A case study in porting a production scientific supercomputing application to a reconfigurable computerFull-text access may be available. Sign in or learn about subscription options.pp. 13-22
Session 1: Supercomputer Applications
Hardware/Software Approach to Molecular Dynamics on Reconfigurable ComputersFull-text access may be available. Sign in or learn about subscription options.pp. 23-34
Session 2: Methodology and Tools
Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 35-44
Session 2: Methodology and Tools
Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C FunctionsFull-text access may be available. Sign in or learn about subscription options.pp. 45-56
Session 3: Data Generation and Processing
Efficient Hardware Generation of Random Variates with Arbitrary DistributionsFull-text access may be available. Sign in or learn about subscription options.pp. 57-66
Session 3: Data Generation and Processing
An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 67-75
Session 3: Data Generation and Processing
Automatic Sliding Window Operation Optimization for FPGA-BasedFull-text access may be available. Sign in or learn about subscription options.pp. 76-88
Session 4: Hybrid Systems
Enabling a Uniform Programming Model Across the Software/Hardware BoundaryFull-text access may be available. Sign in or learn about subscription options.pp. 89-98
Session 4: Hybrid Systems
A Type Architecture for Hybrid Micro-Parallel ComputersFull-text access may be available. Sign in or learn about subscription options.pp. 99-110
Session 5: Multi-processor/Threaded System
A Scalable FPGA-based MultiprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 111-120
An FPGA Solution for Radiation Dose CalculationFull-text access may be available. Sign in or learn about subscription options.pp. 227-236
Session 5: Multi-processor/Threaded System
A Reconfigurable Distributed Computing Fabric Exploiting Multilevel ParallelismFull-text access may be available. Sign in or learn about subscription options.pp. 121-130
Session 5: Multi-processor/Threaded System
A Multithreaded Soft Processor for SoPC Area ReductionFull-text access may be available. Sign in or learn about subscription options.pp. 131-142
Session 6: Graph Algorithms
GraphStep: A System Architecture for Sparse-Graph AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 143-151
Session 6: Graph Algorithms
Hardware/Software Integration for FPGA-based All-Pairs Shortest-PathsFull-text access may be available. Sign in or learn about subscription options.pp. 152-164
Session 7: Power and Energy Optimization
A Field Programmable RFID Tag and Associated Design FlowFull-text access may be available. Sign in or learn about subscription options.pp. 165-174
Session 7: Power and Energy Optimization
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 175-184
Session 7: Power and Energy Optimization
Power Visualization, Analysis, and Optimization Tools for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 185-194
Session 8: Network Technology
Systematic Characterization of Programmable Packet Processing PipelinesFull-text access may be available. Sign in or learn about subscription options.pp. 195-204
Session 8: Network Technology
Packet Switched vs. Time Multiplexed FPGA Overlay NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 205-216
Session 9: Biomedical and Cryptographic Applications
Single Pass, BLAST-Like, Approximate String Matching on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 217-226
A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)Full-text access may be available. Sign in or learn about subscription options.pp. 237-248
Session 10: Arithmetic
Advanced Components in the Variable Precision Floating-Point LibraryFull-text access may be available. Sign in or learn about subscription options.pp. 249-258
Session 10: Arithmetic
Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision ComponentsFull-text access may be available. Sign in or learn about subscription options.pp. 259-270
Posters
ASC-Based Acceleration in an FPGA with a Processor Core Using Software-Only SkillsFull-text access may be available. Sign in or learn about subscription options.pp. 271-272
Posters
COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 273-274
Posters
A Novel Hueristic and Provable Bounds for Reconfigurable Architecture DesignFull-text access may be available. Sign in or learn about subscription options.pp. 275-276
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Defect-Tolerant Nanocomputing Using Bloom FiltersFull-text access may be available. Sign in or learn about subscription options.pp. 277-278
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A Programmable, Maximal Throughput Architecture for Neighborhood Image ProcessingFull-text access may be available. Sign in or learn about subscription options.pp. 279-280
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VPN Acceleration Using Reconfigurable System-On-Chip TechnologyFull-text access may be available. Sign in or learn about subscription options.pp. 281-282
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An Optimized Finite Difference Computing Engine on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 283-284
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Highly Efficient String Matching Circuit for IDS with FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 285-286
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Effects of High-Level Discrete Signal Transform Formulations on Partitioning for Multi-FPGA ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 287-288
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Scheduling divisible loads on partially reconfigurable hardwareFull-text access may be available. Sign in or learn about subscription options.pp. 289-290
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General Architecture for Hardware Implementation of Genetic AlgorithmFull-text access may be available. Sign in or learn about subscription options.pp. 291-292
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Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 293-294
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Scalable Softcore Vector Processor for Biosequence ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 295-296
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Generating Parametrised Hardware Libraries from Higher-Order DescriptionsFull-text access may be available. Sign in or learn about subscription options.pp. 297-298
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Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM)Full-text access may be available. Sign in or learn about subscription options.pp. 299-300
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Floating-Point Accumulation Circuit for Matrix ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 303-304
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Application-Specific Memory Interleaving Enables High Performance in FPGA-based Grid ComputationsFull-text access may be available. Sign in or learn about subscription options.pp. 305-306
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A Task Graph Approach for Efficient Exploitation of Reconfiguration in Dynamically Reconfigurable SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 307-308
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A Low-Energy Reconfigurable Fabric for the SuperCISC ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 309-310
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COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-BreakingFull-text access may be available. Sign in or learn about subscription options.pp. 311-312
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FPGAs, GPUs and the PS2 - A Single Programming MethodologyFull-text access may be available. Sign in or learn about subscription options.pp. 313-314
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Integrating FPGA Acceleration into the Protomol Molecular Dynamics Code: Preliminary ReportFull-text access may be available. Sign in or learn about subscription options.pp. 315-316
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A Co-Verification Tool for a High Level Language Compiler for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 317-318
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Intrinsic Hardware Evolution of Neural Networks in Reconfigurable Analogue and Digital DevicesFull-text access may be available. Sign in or learn about subscription options.pp. 321-322
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The STAR-C Truth: Analyzing Reconfigurable Supercomputing ReliabilityFull-text access may be available. Sign in or learn about subscription options.pp. 323-324
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Pre-synthesis Queue Size Estimation of Streaming Data Flow GraphsFull-text access may be available. Sign in or learn about subscription options.pp. 325-326
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Hierarchical Clustering using Reconfigurable DevicesFull-text access may be available. Sign in or learn about subscription options.pp. 327-328
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CAD Tool for FPGAs with Embedded Hard Cores for Design Space Exploration of Future ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 329-330
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A Scalable Architecture for RSA Cryptography on Large FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 331-332
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Design of a Reconfigurable Processor for NIST Prime Field ECCFull-text access may be available. Sign in or learn about subscription options.pp. 333-334
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Switch Box Architectures for Three-Dimensional FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 335-336
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A Scalable Hybrid Regular Expression Pattern MatcherFull-text access may be available. Sign in or learn about subscription options.pp. 337-338
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Hardware/Software Co-Design Architecture for Lattice Decoding AlgorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 339-340
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High Performance Feature Detection on a Reconfigurable Co-ProcessorFull-text access may be available. Sign in or learn about subscription options.pp. 341-342
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DSynth: A Pipeline Synthesis Environment for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 343-344
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Template-Based Generation of Streaming Accelators from a High Level PresentationFull-text access may be available. Sign in or learn about subscription options.pp. 345-346
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Scalable Hardware Architecture for Real-Time Dynamic Programming ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 347-348
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Open Source High Performance Floating-Point ModulesFull-text access may be available. Sign in or learn about subscription options.pp. 349-350
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A Reconfigurable Cluster-on-Chip Architecture with MPI Communication LayerFull-text access may be available. Sign in or learn about subscription options.pp. 351-352
Author Index
Author IndexFreely available from IEEE.pp. 353
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