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Field-Programmable Custom Computing Machines, Annual IEEE Symposium on

May 1 2011 to May 3 2011

Salt Lake City, Utah USA

ISBN: 978-0-7695-4301-7

Table of Contents

Papers
Architecture, Design, and Experimental Evaluation of a Lightfield Descriptor Depth Buffer Algorithm on Reconfigurable Logic and on a GPUFull-text access may be available. Sign in or learn about subscription options.pp. 57-64
Papers
Title Page iFreely available from IEEE.pp. i
Papers
Title Page iiiFreely available from IEEE.pp. iii
Papers
[Copyright notice]Freely available from IEEE.pp. iv
Papers
Table of contentsFreely available from IEEE.pp. v-ix
Papers
Message from the General and Program ChairsFreely available from IEEE.pp. x-xi
Papers
Organizing CommitteeFreely available from IEEE.pp. xii
Papers
Program CommitteeFreely available from IEEE.pp. xiii-xiv
Papers
Additional ReviewersFreely available from IEEE.pp. xv
Preconference Workshop SummaryFreely available from IEEE.pp. xvi-xvi
Preconference Workshop SummaryFreely available from IEEE.pp. xvi-xvi
Papers
Panel Session SummaryFreely available from IEEE.pp. xvii-xvii
Papers
A Sparse Matrix Personality for the Convey HC-1Full-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Krishna K. Nagar, Jason D. Bakos
Papers
Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional VerificationFull-text access may be available. Sign in or learn about subscription options.pp. 9-16
by Lingkan Gong, Oliver Diessel
Papers
Mixed Precision Processing in Reconfigurable SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 17-24
by Gary C.T. Chow, K.W. Kwok, Wayne Luk, Philip Leong
Papers
Dynamic Communication in a Coarse Grained Reconfigurable ArrayFull-text access may be available. Sign in or learn about subscription options.pp. 25-28
by Robin Panda, Scott Hauck
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Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 29-32
by Waheed Ahmed, Muhammad Shafique, Lars Bauer, Manuel Hammerich, Jörg Henkel, Juergen Becker
Papers
An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 33-36
by Jainik Kathiara, Miriam Leeser
Papers
Hecto-Scale Frame Rate Face Detection System for SVGA Source on FPGA BoardFull-text access may be available. Sign in or learn about subscription options.pp. 37-40
by Zheng Ding, Feng Zhao, Tinghui Wang, Wei Shu, Min-You Wu
Papers
An FPGA Implementation of Information Theoretic Visual-Saliency System and Its OptimizationFull-text access may be available. Sign in or learn about subscription options.pp. 41-48
by Sungmin Bae, Yong Cheol Peter Cho, Sungho Park, Kevin M. Irick, Yongseok Jin, Vijaykrishnan Narayanan
Papers
Scalable, High Performance Fourier Domain Optical Coherence Tomography: Why FPGAs and Not GPGPUsFull-text access may be available. Sign in or learn about subscription options.pp. 49-56
by Jian Li, Marinko V. Sarunic, Lesley Shannon
Papers
Implementation and Performance Analysis of SEAL Encryption on FPGA, GPU and Multi-core ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 65-68
by Kostas Theoharoulis, Charalambos Antoniadis, Nikolaos Bellas, Christos D. Antonopoulos
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FPGA Communication FrameworkFull-text access may be available. Sign in or learn about subscription options.pp. 69-72
by Peter Lieber, Brad Hutchings
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Efficient Calculation of Pairwise Nonbonded ForcesFull-text access may be available. Sign in or learn about subscription options.pp. 73-76
by Matt Chiu, Md. Ashfaquzzaman Khan, Martin C. Herbordt
Papers
High Performance IP Lookup on FPGA with Combined Length-Infix Pipelined SearchFull-text access may be available. Sign in or learn about subscription options.pp. 77-80
by Yi-Hua E. Yang, Oguzhan Erdem, Viktor K. Prasanna
Papers
A Scalable Multi-FPGA Platform for Complex Networking ApplicationsFull-text access may be available. Sign in or learn about subscription options.pp. 81-84
by Sascha Mühlbach, Andreas Koch
Papers
An FPGA-Based Optical IOH Architecture for Embedded SystemFull-text access may be available. Sign in or learn about subscription options.pp. 85-88
by Liu Ling, Zhuang Jincan, Zhu Qianying, Zhu Shunyu, Zhang Zhiyuan, Zhang Xinxin, Cao Lu, Yu Zhihong, Wu Xiangbin, Liu Dong
Papers
On Comparing Financial Option Price Solvers on FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 89-92
by Qiwei Jin, Wayne Luk, David B. Thomas
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Low-Latency FPGA Based Financial Data Feed HandlerFull-text access may be available. Sign in or learn about subscription options.pp. 93-96
by Robin Pottathuparambil, Jack Coyne, Jeffrey Allred, William Lynch, Vincent Natoli
Papers
Design and Implementation of an FPGA-Based Real-Time Face Recognition SystemFull-text access may be available. Sign in or learn about subscription options.pp. 97-100
by Janarbek Matai, Ali Irturk, Ryan Kastner
Papers
FPGA-Based Solid-State Drive Prototyping PlatformFull-text access may be available. Sign in or learn about subscription options.pp. 101-104
by Yu Cai, Erich F. Haratsch, Mark McCartney, Ken Mai
Papers
Accelerating Statistical LOR Estimation for a High-Resolution PET Scanner Using FPGA Devices and a High Level Synthesis ToolFull-text access may be available. Sign in or learn about subscription options.pp. 105-108
by Zhong-Ho Chen, Alvin W.Y. Su, Ming-Ting Sun, Scott Hauck
Papers
SYSCORE: A Coarse Grained Reconfigurable Array Architecture for Low Energy Biosignal ProcessingFull-text access may be available. Sign in or learn about subscription options.pp. 109-112
by Kunjan Patel, Séamas McGettrick, Chris J. Bleakley
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High-Throughput, Lossless Data Compresion on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 113-116
by Bharat Sukhwani, Bulent Abali, Bernard Brezzo, Sameh Asaad
Papers
HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid PrototypingFull-text access may be available. Sign in or learn about subscription options.pp. 117-124
by Christopher Lavin, Marc Padilla, Jaren Lamprecht, Philip Lundrigan, Brent Nelson, Brad Hutchings
Papers
Automatic HDL-Based Generation of Homogeneous Hard Macros for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 125-132
by Sebastian Korf, Dario Cozzi, Markus Koester, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert, Marco D. Santambrogio
Papers
Using Functional Programming to Generate an LDPC Forward Error CorrectorFull-text access may be available. Sign in or learn about subscription options.pp. 133-140
by Andy Gill, Tristan Bull, Dan DePardo, Andrew Farmer, Ed Komp, Erik Perrins
Papers
Reconfigurable Data Processing for CloudsFull-text access may be available. Sign in or learn about subscription options.pp. 141-145
by Anil Madhavapeddy, Satnam Singh
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TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory SystemFull-text access may be available. Sign in or learn about subscription options.pp. 146-153
by Nehir Sonmez, Oriol Arcas, Otto Pflucker, Osman S. Unsal, Adri´n Cristal, Ibrahim Hur, Satnam Singh, Mateo Valero
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The PowerPC 405 Memory Sentinel and Injection SystemFull-text access may be available. Sign in or learn about subscription options.pp. 154-161
by Mark Bucciero, John Paul Walters, Roger Moussalli, Shanyuan Gao, Matthew French
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Checkpoint/Restart and Beyond: Resilient High Performance Computing with FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 162-169
by Andrew G. Schmidt, Bin Huang, Ron Sass, Matthew French
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FUSE: Front-End User Framework for O/S Abstraction of Hardware AcceleratorsFull-text access may be available. Sign in or learn about subscription options.pp. 170-177
by Aws Ismail, Lesley Shannon
Papers
Multilevel Granularity Parallelism Synthesis on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 178-185
by Alexandros Papakonstantinou, Yun Liang, John A. Stratton, Karthik Gururaj, Deming Chen, Wen-Mei W. Hwu, Jason Cong
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Synthesis of Platform Architectures from OpenCL ProgramsFull-text access may be available. Sign in or learn about subscription options.pp. 186-193
by Muhsen Owaida, Nikolaos Bellas, Konstantis Daloukas, Christos D. Antonopoulos
Papers
Programming Real-Time Autofocus on a Massively Parallel Reconfigurable Architecture Using Occam-piFull-text access may be available. Sign in or learn about subscription options.pp. 194-201
by Zain-ul-Abdin, Anders Ahlander, Bertil Svensson
Papers
Towards Synthesis-Free JIT Compilation to Commodity FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 202-205
by Davor Capalija, Tarek S. Abdelrahman
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Automated Placement for Parallelized FPGA FFTsFull-text access may be available. Sign in or learn about subscription options.pp. 206-209
by Suraj Gowda, Aaron Parsons, Robert Jarnot, Dan Werthimer
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Reducing the Energy Cost of Irregular Code Bases in Soft Processor SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 210-213
by Manish Arora, Jack Sampson, Nathan Goulding-Hotta, Jonathan Babb, Ganesh Venkatesh, Michael Bedford Taylor, Steven Swanson
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Extending Force-Directed Scheduling with Explicit Parallel and Timed Constructs for High-Level SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 214-217
by Rohit Sinha, Hiren D. Patel
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String Matching in Hardware Using the FM-IndexFull-text access may be available. Sign in or learn about subscription options.pp. 218-225
by Edward Fernandez, Walid Najjar, Stefano Lonardi
Papers
Accelerating Phylogeny-Aware Short DNA Read Alignment with FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 226-233
by Nikolaos Alachiotis, Simon A. Berger, Alexandros Stamatakis
Papers
Scalable Streaming-Array of Simple Soft-Processors for Stencil Computations with Constant Memory-BandwidthFull-text access may be available. Sign in or learn about subscription options.pp. 234-241
by Kentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto
Papers
Memory-Efficient IPv4/v6 Lookup on FPGAs Using Distance-Bounded Path CompressionFull-text access may be available. Sign in or learn about subscription options.pp. 242-249
by Hoang Le, Weirong Jiang, Viktor K. Prasanna
Papers
A Key Size Configurable High Speed RSA CoprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 250
by E. Castillo, J. Castillo, J. Cano, P. Huerta, J.I. Martínez
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A Model for Peak Matrix Performance on FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 251
by Colin Y. Lin, Hayden K.-H. So, Philip H.W. Leong
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Reconsideration of Computing Paradigms and a Novel Reconfigurable ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 252
by Ming Yan, Ziyu Yang, Sikun Li, Liu Yang
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Hybrid Data Structure for IP Lookup in Virtual Routers Using FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 253
by Oguzhan Erdem, Hoang Le, Viktor Prasanna, Cüneyt F. Bazlamaçci
Papers
FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking ActivitiesFull-text access may be available. Sign in or learn about subscription options.pp. 254
by Will X.Y. Li, Ray C.C. Cheung, Wei Zhang, Rosa H.M. Chan, Dong Song, Theodore W. Berger
Papers
Implementation and Performance Comparison of the Motion Compensation Kernel of the AVS Video Decoder on FPGA, GPU and Multicore ProcessorsFull-text access may be available. Sign in or learn about subscription options.pp. 255
by M. Owaida, N. Bellas, C.D. Antonopoulos, K. Daloukas, Ch. Antoniadis, K. Krommydas, G. Tsoumblekas
Papers
Author IndexFreely available from IEEE.pp. 256-258
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[Publishers information]Freely available from IEEE.pp. 260
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