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2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

April 30 2017 to May 2 2017

Napa, CA

Table of Contents

pp. i-i

[Title page iii]

pp. iii-iii

[Copyright notice]

pp. iv-iv

Table of contents

pp. v-ix

A Message from the General Chair and Program Chair

pp. x-xi

Program Committee

pp. xii-xiii

Additional Reviewers

pp. xiv-xiv

High-Performance Hardware Merge Sorter

pp. 1-8

by Susumu Mashimo, Thiem Van Chu, Kenji Kise

Communication-Aware MCMC Method for Big Data Applications on FPGAs

pp. 9-16

by Shuanglong Liu, Christos-Savvas Bouganis

Terabyte Sort on FPGA-Accelerated Flash Storage

pp. 17-24

by Sang-Woo Jun, Shuotao Xu, Arvind

Improved Synthesis of Compressor Trees on FPGAs in High-Level Synthesis

pp. 25-25

by Le Tu, Yuelai Yuan, Kan Huang, Xiaoqiang Zhang, Zixin Wang, Dihu Chen

SWiF: A Simplified Workload-Centric Framework for FPGA-Based Computing

pp. 26-26

by David Ojika, Piotr Majcher, Wojciech Neubauer, Suchit Subhaschandra, Darin Acosta

Megrez: Parallelizing FPGA Routing with Strictly-Ordered Partitioning

pp. 27-27

by Minghua Shen, Guojie Luo

An FPGA Design Framework for CNN Sparsification and Acceleration

pp. 28-28

by Sicheng Li, Wei Wen, Yu Wang, Song Han, Yiran Chen, Hai Li

FPGA Delay Model Considering Logic-Level and Transistor-Level Parameters

pp. 29-29

by Qiang Liu, Hanjing Qian

Scheduling Considerations for Voter Checking in TMR-MER Systems

pp. 30-30

by Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel

Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA

pp. 31-31

by Jianxin Guo, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei

On Bit-Serial NoCs for FPGAs

pp. 32-39

by Nachiket Kapre

Implementing FPGA Overlay NoCs Using the Xilinx UltraScale Memory Cascades

pp. 40-47

by Nachiket Kapre

Efficient GPGPU Computing with Cross-Core Resource Sharing and Core Reconfiguration

pp. 48-55

by Ashutosh Dhar, Deming Chen

An Architecture for the Acceleration of a Hybrid Leaky Integrate and Fire SNN on the Convey HC-2ex FPGA-Based Processor

pp. 56-63

by Emmanouil Kousanakis, Apostolos Dollas, Euripides Sotiriades, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos, Athanasia Papoutsi, Panagiotis C. Petrantonakis, Panayiota Poirazi, Spyridon Chavlis, George Kastellakis

FPGA-Based Real-Time Charged Particle Trajectory Reconstruction at the Large Hadron Collider

pp. 64-71

by Edward Bartz, Jorge Chaves, Yuri Gershtein, Eva Halkiadakis, Michael Hildreth, Savvas Kyriacou, Kevin Lannon, Anthony Lefeld, Anders Ryd, Louise Skinnari, Robert Stone, Charles Strohman, Zhengcheng Tao, Brian Winer, Peter Wittich, Zhiru Zhang, Margaret Zientek

Bonded Force Computations on FPGAs

pp. 72-75

by Qingqing Xiong, Martin C. Herbordt

Efficient Particle-Grid Space Interpolation of an FPGA-Accelerated Particle-in-Cell Plasma Simulation

pp. 76-79

by Almomany Abedalmuhdi, B. Earl Wells, Ken-Ichi Nishikawa

A High-Level Synthesis Approach Optimizing Accumulations in Floating-Point Programs Using Custom Formats and Operators

pp. 80-80

by Yohann Uguen, Florent de Dinechin, Steven Derrien

A Case for Common-Case: On FPGA Acceleration of Erasure Coding

pp. 81-81

by Reza Nakhjavani, Jianwen Zhu

Accelerating Large-Scale Graph Analytics with FPGA and HMC

pp. 82-82

by Soroosh Khoram, Jialiang Zhang, Maxwell Strange, Jing Li

Fast and Energy-Driven Design Space Exploration for Heterogeneous Architectures

pp. 83-83

by Baptiste Roux, Matthieu Gautier, Olivier Sentieys, Jean-Philippe Delahaye

A Parameterizable Activation Function Generator for FPGA-Based Neural Network Applications

pp. 84-84

by Sam M. H. Ho, C.-H. Dominic Hung, Ho-Cheung Ng, Maolin Wang, Hayden Kwok-Hay So

Customizing Neural Networks for Efficient FPGA Implementation

pp. 85-92

by Mohammad Samragh, Mohammad Ghasemzadeh, Farinaz Koushanfar

Escher: A CNN Accelerator with Flexible Buffering to Minimize Off-Chip Transfer

pp. 93-100

by Yongming Shen, Michael Ferdman, Peter Milder

Evaluating Fast Algorithms for Convolutional Neural Networks on FPGAs

pp. 101-108

by Liqiang Lu, Yun Liang, Qingcheng Xiao, Shengen Yan

Using Runahead Execution to Hide Memory Latency in High Level Synthesis

pp. 109-116

by Shane T. Fleming, David B. Thomas

Energy Efficient Loop Unrolling for Low-Cost FPGAs

pp. 117-120

by Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel Holcomb, Russell Tessier

Evaluating Rapid Application Development with Python for Heterogeneous Processor-Based FPGAs

pp. 121-124

by Andrew G. Schmidt, Gabriel Weisz, Matthew French

HLScope: High-Level Performance Debugging for FPGA Designs

pp. 125-128

by Young-Kyu Choi, Jason Cong

TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS

pp. 129-132

by Ganghee Lee, Dimitris Agiakatsikas, Tong Wu, Ediz Cetin, Oliver Diessel

Exploration of FPGA-Based Packet Switches for Rack-Scale Computers on a Board

pp. 133-133

by Jong Hun Han, Neelakandan Manihatty-Bojan, Andrew W. Moore

An Out-of-Order Load-Store Queue for Spatial Computing

pp. 134-134

by Lana Josipovic, Philip Brisk, Paolo Ienne

Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA

pp. 135-135

by Philip Colangelo, Randy Huang, Enno Luebbers, Martin Margala, Kevin Nealis

Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices

pp. 136-143

by Jeffrey Goeders

The Potential of Dynamic Binary Modification and CPU-FPGA SoCs for Simulation

pp. 144-151

by John Mawer, Oscar Palomar, Cosmin Gorgovan, Andy Nisbet, Will Toms, Mikel Luján

FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates

pp. 152-159

by Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong

FPGA-Accelerated Dense Linear Machine Learning: A Precision-Convergence Trade-Off

pp. 160-167

by Kaan Kara, Dan Alistarh, Gustavo Alonso, Onur Mutlu, Ce Zhang

A Configurable FPGA Implementation of the Tanh Function Using DCT Interpolation

pp. 168-171

by Ahmed M. Abdelsalam, J. M. Pierre Langlois, F. Cheriet

ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding

pp. 172-179

by Chin Hau Hoo, Akash Kumar

Automata-to-Routing: An Open-Source Toolchain for Design-Space Exploration of Spatial Automata Processing Architectures

pp. 180-187

by Jack Wadden, Samira Khan, Kevin Skadron

Relocating Encrypted Partial Bitstreams by Advance Task Address Loading

pp. 188-191

by Adewale Adetomi, Godwin Enemali, Tughrul Arslan

CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing

pp. 192-192

by Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima

Multi-FPGA Evaluation Platform for Disaggregated Computing

pp. 193-193

by Dimitris Theodoropoulos, Nikolaos Alachiotis, Dionisios Pnevmatikatos

Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAs

pp. 194-194

by Fubing Mao, Wei Zhang, Bingsheng He, Siew-Kei Lam

Exploring High Efficiency Hardware Accelerator for the Key Algorithm of Square Kilometer Array Telescope Data Processing

pp. 195-195

by Qian Wu, Yongxin Zhu, Xu Wang, Mengjun Li, Junjie Hou, Ali Masoumi

Minimalist Design for Accelerating Convolutional Neural Networks for Low-End FPGA Platforms

pp. 196-196

by Raghid Morcel, Haitham Akkary, Hazem Hajj, Mazen Saghir, Anil Keshavamurthy, Rahul Khanna, Hassan Artail

A Network-on-Chip Based H.264 Video Decoder Prototype Implemented on FPGAs

pp. 197-197

by Ian J. Barge, Cristinel Ababei

Applying the Flask Security Architecture to Secure SoC Design

pp. 198-198

by Festus Hategekimana, Christophe Bobda

A Real-Time Embedded FPGA Processor for a Stand-Alone Dual-Mode Assistive Device

pp. 199-199

by Ali Jafari, Maysam Ghovanloo, Tinoosh Mohsenin

CAPSL: A Tool for Automatic Generation of Hardware Sandboxes for IP Security

pp. 200-200

by Taylor JL Whitaker, Christophe Bobda

A Scalable FPGA-Based Accelerator for High-Throughput MCMC Algorithms

pp. 201-201

by Morteza Hosseini, Rashidul Islam, Amey Kulkarni, Tinoosh Mohsenin

Improving the Accuracy of Arctan for Face Detection

pp. 202-202

by Youngsoo Kim, Hossein Shahdoost, Shrikant Jadhav, Clay S. Gloster

K-Mer Counting Using Bloom Filters with an FPGA-Attached HMC

pp. 203-210

by Nathaniel Mcvicar, Chih-Ching Lin, Scott Hauck

Centaur: A Framework for Hybrid CPU-FPGA Databases

pp. 211-218

by Muhsen Owaida, David Sidler, Kaan Kara, Gustavo Alonso

Scalable Network Function Virtualization for Heterogeneous Middleboxes

pp. 219-226

by Xuzhi Zhang, Xiaozhe Shao, George Provelengios, Naveen Kumar Dumpala, Lixin Gao, Russell Tessier

A Nanosecond–Level Hybrid Table Design for Financial Market Data Generators

pp. 227-234

by Haohuan Fu, Conghui He, Wayne Luk, Weijia Li, Guangwen Yang

pp. 235-237

[Publisher's information]

pp. 238-238

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