1. Home
  2. Proceedings
  3. FCCM
  4. FCCM 2018
Default Cover Image

2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

April 29 2018 to May 1 2018

Boulder, CO, USA

Table of Contents

Title Page iFreely available from IEEE.pp. 1-1
Title Page iiiFreely available from IEEE.pp. 3-3
Copyright PageFreely available from IEEE.pp. 4-4
Table of ContentsFreely available from IEEE.pp. 5-11
Message from the FCCM 2018 General and Program ChairsFreely available from IEEE.pp. 12-13
FCCM 2018 Organizing CommitteeFreely available from IEEE.pp. 14-14
FCCM 2018 Program CommitteeFreely available from IEEE.pp. 15-16
FCCM 2018 Additional ReviewersFreely available from IEEE.pp. 17-17
FCCM 2018 SponsorsFreely available from IEEE.pp. 18-19
Evaluating the Performance Efficiency of a Soft-Processor, Variable-Length, Parallel-Execution-Unit Architecture for FPGAs Using the RISC-V ISAFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Eric Matthews, Zavier Aguila, Lesley Shannon
ST-Accel: A High-Level Programming Platform for Streaming Applications on FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 9-16
by Zhenyuan Ruan, Tong He, Bojie Li, Peipei Zhou, Jason Cong
Hoplite-Q: Priority-Aware Routing in FPGA Overlay NoCsFull-text access may be available. Sign in or learn about subscription options.pp. 17-24
by Siddhartha ., Nachiket Kapre
A Bandwidth-Optimized Routing Algorithm for Hybrid FPGA Networks-on-ChipFull-text access may be available. Sign in or learn about subscription options.pp. 25-28
by Shivukumar B. Patil, Tianqi Liu, Russell Tessier
Improved Lightweight Implementations of CAESAR Authenticated CiphersFull-text access may be available. Sign in or learn about subscription options.pp. 29-36
by Farnoud Farahmand, William Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj
High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA PlatformsFull-text access may be available. Sign in or learn about subscription options.pp. 37-44
by Weikang Qiao, Jieqiong Du, Zhenman Fang, Michael Lo, Mau-Chung Frank Chang, Jason Cong
FPGA Side Channel Attacks without Physical AccessFull-text access may be available. Sign in or learn about subscription options.pp. 45-52
by Chethan Ramesh, Shivukumar B. Patil, Siva Nishok Dhanuskodi, George Provelengios, Sebastien Pillement, Daniel Holcomb, Russell Tessier
Inheriting Software Security Policies within Hardware IP ComponentsFull-text access may be available. Sign in or learn about subscription options.pp. 53-56
by Festus Hategekimana, Joel Mandebi Mbongue, Md Jubaer Hossain Pantho, Christophe Bobda
ReBNet: Residual Binarized Neural NetworkFull-text access may be available. Sign in or learn about subscription options.pp. 57-64
by Mohammad Ghasemzadeh, Mohammad Samragh, Farinaz Koushanfar
FlexiGAN: An End-to-End Solution for FPGA Acceleration of Generative Adversarial NetworksFull-text access may be available. Sign in or learn about subscription options.pp. 65-72
by Amir Yazdanbakhsh, Michael Brzozowski, Behnam Khaleghi, Soroush Ghodrati, Kambiz Samadi, Nam Sung Kim, Hadi Esmaeilzadeh
Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 73-80
by Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit Mishra, Martin Margala, Kevin Nealis
FPDeep: Acceleration and Load Balancing of CNN Training on FPGA ClustersFull-text access may be available. Sign in or learn about subscription options.pp. 81-84
by Tong Geng, Tianqi Wang, Ahmed Sanaullah, Chen Yang, Rui Xu, Rushi Patel, Martin Herbordt
Hot & Spicy: Improving Productivity with Python and HLS for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 85-92
by Sam Skalicky, Joshua Monson, Andrew Schmidt, Matthew French
Understanding Performance Differences of FPGAs and GPUsFull-text access may be available. Sign in or learn about subscription options.pp. 93-96
by Jason Cong, Zhenman Fang, Michael Lo, Hanrui Wang, Jingxian Xu, Shaochong Zhang
High-Frequency Absorption-FIFO Pipelining for Stratix 10 HyperFlexFull-text access may be available. Sign in or learn about subscription options.pp. 97-100
by Madison N. Emas, Austin Baylis, Greg Stitt
Concurrency-Aware Thread Scheduling for High-Level SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 101-108
by Nadesh Ramanathan, George A. Constantinides, John Wickerson
High-Level Synthesis of FPGA Circuits with Multiple Clock DomainsFull-text access may be available. Sign in or learn about subscription options.pp. 109-116
by Omar Ragheb, Jason H. Anderson
LegUp-NoC: High-Level Synthesis of Loops with Indirect AddressingFull-text access may be available. Sign in or learn about subscription options.pp. 117-124
by Asif Islam, Nachiket Kapre
Latte: Locality Aware Transformation for High-Level SynthesisFull-text access may be available. Sign in or learn about subscription options.pp. 125-128
by Jason Cong, Peng Wei, Cody Hao Yu, Peipei Zhou
Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine LearningFull-text access may be available. Sign in or learn about subscription options.pp. 129-132
by Steve Dai, Yuan Zhou, Hang Zhang, Ecenur Ustun, Evangeline F.Y. Young, Zhiru Zhang
RapidWright: Enabling Custom Crafted Implementations for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 133-140
by Chris Lavin, Alireza Kaviani
Improving the Effectiveness of TMR Designs on FPGAs with SEU-Aware Incremental PlacementFull-text access may be available. Sign in or learn about subscription options.pp. 141-148
by Matthew Cannon, Andrew Keller, Michael Wirthlin
Demand Driven Assembly of FPGA Configurations Using Partial Reconfiguration, Ubuntu Linux, and PYNQFull-text access may be available. Sign in or learn about subscription options.pp. 149-156
by Jeffrey Goeders, Tanner Gaskin, Brad Hutchings
HODS: Hardware Object Deserialization Inside SSD StorageFull-text access may be available. Sign in or learn about subscription options.pp. 157-164
by Dongyang Li, Fei Wu, Yang Weng, Qing Yang, Changsheng Xie
CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA PlatformsFull-text access may be available. Sign in or learn about subscription options.pp. 165-172
by Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang
Microscope on Memory: MPSoC-Enabled Computer Memory System AssessmentsFull-text access may be available. Sign in or learn about subscription options.pp. 173-180
by Abhishek Kumar Jain, Scott Lloyd, Maya Gokhale
FPGA-Based Real-Time Super-Resolution System for Ultra High Definition VideosFull-text access may be available. Sign in or learn about subscription options.pp. 181-188
by Zhuolun He, Hanxian Huang, Ming Jiang, Yuanchao Bai, Guojie Luo
OpenCL-Based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured MeshesFull-text access may be available. Sign in or learn about subscription options.pp. 189-196
by Tobias Kenter, Gopinath Mahale, Samer Alhaddad, Yevgen Grynko, Christian Schmitt, Ayesha Afzal, Frank Hannig, Jens Förstner, Christian Plessl
A High-Performance and Cost-Effective Hardware Merge Sorter without Feedback DatapathFull-text access may be available. Sign in or learn about subscription options.pp. 197-204
by Makoto Saitoh, Elsayed A. Elsayed, Thiem Van Chu, Susumu Mashimo, Kenji Kise
EM-Aware Memory Mapping Algorithms for SRAM Based FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 205-205
by Zhong Guan
SMEM++: A Pipelined and Time-Multiplexed SMEM Seeding Accelerator for DNA SequencingFull-text access may be available. Sign in or learn about subscription options.pp. 206-206
by Jason Cong, Licheng Guo, Po-Tsang Huang, Peng Wei, Tianhe Yu
PQ-CNN: Accelerating Product Quantized Convolutional Neural Network on FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 207-207
by Jialiang Zhang, Jing Li
NewGraph: Balanced Large-Scale Graph Processing on FPGAs with Low Preprocessing OverheadsFull-text access may be available. Sign in or learn about subscription options.pp. 208-208
by Guhao Dai, Tianhao Huang, Yu Wang, Huazhong Yang, John Wawrzynek
Exploiting Box Expansion and Grid Partitioning for Parallel FPGA RoutingFull-text access may be available. Sign in or learn about subscription options.pp. 209-209
by Minghua Shen, Guojie Luo, Nong Xiao
AccDNN: An IP-Based DNN Generator for FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 210-210
by Xiaofan Zhang, Junsong Wang, Chao Zhu, Yonghua Lin, Jinjun Xiong, Wen-mei Hwu, Deming Chen
Reloc — An Open-Source Vivado Workflow for Generating Relocatable End-User Configuration TilesFull-text access may be available. Sign in or learn about subscription options.pp. 211-211
by Björn Gottschall, Thomas Preußer, Akash Kumar
From C to Fault-Tolerant FPGA-Based SystemsFull-text access may be available. Sign in or learn about subscription options.pp. 212-212
by Dimitris Agiakatsikas, Ganghee Lee, Thomas Mitchell, Ediz Cetin, Oliver Diessel
Wibheda: Framework for Data Dependency-Aware Multi-Constrained Hardware-Software Partitioning in FPGA-Based SoCs for IoT DevicesFull-text access may be available. Sign in or learn about subscription options.pp. 213-213
by Deshya Wijesundera, Alok Prakash, Thilina Perera, Kalindu Herath, Thambipillai Srikanthan
High-Speed Regular Expression Matching with Pipelined Memory-Based AutomataFull-text access may be available. Sign in or learn about subscription options.pp. 214-214
by Denis Matousek, Jirí Matousek, Jan Korenek
Rethinking Secure FPGAs: Towards a Cryptography-Friendly Configurable Cell Architecture and Its Automated Design FlowFull-text access may be available. Sign in or learn about subscription options.pp. 215-215
by Nele Mentens, Edoardo Charbon, Francesco Regazzoni
A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid MediaFull-text access may be available. Sign in or learn about subscription options.pp. 216-216
by Abdul-Amir Yassine, Yasmin Afsharnejad, Omar Ragheb, Vaughn Betz, Paul Chow
Enabling Transparent Acceleration of OpenCV Library Kernels on a Hybrid Memory Cube ComputerFull-text access may be available. Sign in or learn about subscription options.pp. 217-217
by Md Jubaer Hossain Pantho, Joel Mandebi Mbongue, Christophe Bobda, David Andrews, Marjan Asadinia
Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGAFull-text access may be available. Sign in or learn about subscription options.pp. 218-218
by Sunwoong Kim, Rob Rutenbar
High Performance Dynamic Communication on Reconfigurable ClustersFull-text access may be available. Sign in or learn about subscription options.pp. 219-219
by Jiayi Sheng, Chen Yang, Tianqi Wang, Martin Herbordt
Performance Prediction for Large-Scale Heterogeneous PlatformsFull-text access may be available. Sign in or learn about subscription options.pp. 220-220
by Ryota Yasudo, Ana L. Varbanescu, José G. F. Coutinho, Wayne Luk, Hideharu Amano
Design Space Exploration for Hardware Acceleration of Machine Learning Applications in MapReduceFull-text access may be available. Sign in or learn about subscription options.pp. 221-221
by Katayoun Neshatpour, Hosein Mohammadi Makrani, Avesta Sasan, Hassan Ghasemzadeh, Setareh Rafatirad, Houman Homayoun
Efficient FPGA Implementation of Binary Field Multipliers Based on Irreducible TrinomialsFull-text access may be available. Sign in or learn about subscription options.pp. 222-222
by José L. Imaña
A PYNQ-Based Framework for Rapid CNN PrototypingFull-text access may be available. Sign in or learn about subscription options.pp. 223-223
by Erwei Wang, James J. Davis, Peter Y. K. Cheung
Automatic Offloading of Cluster AcceleratorsFull-text access may be available. Sign in or learn about subscription options.pp. 224-224
by Ciro Ceissler, Ramon Nepomuceno, Marcio Pereira, Guido Araujo
Cross Component Optimization for Modern LTE Downlink Shared Channel ImplementationFull-text access may be available. Sign in or learn about subscription options.pp. 225-225
by Jieming Xu, Miriam Leeser
Bridging the Gap between Advanced Memory and Heterogeneous ArchitecturesFull-text access may be available. Sign in or learn about subscription options.pp. 226-226
by Abhi D.R., Ron Sass, Andrew Schmidt, Matthew French
Acceleration Framework for FPGA Implementation of OpenVX Graph PipelinesFull-text access may be available. Sign in or learn about subscription options.pp. 227-227
by Sajjad Taheri, Jin Heo, Payman Behnam, Jeffrey Chen, Alexander Veidenbaum, Alexandru Nicolau
Automatic Interior I/O Elimination in Systolic Array ArchitectureFull-text access may be available. Sign in or learn about subscription options.pp. 228-228
by Jason Cong, Jie Wang
Author IndexFreely available from IEEE.pp. 229-231
[Publisher's information]Freely available from IEEE.pp. 232-232
Showing 64 out of 64