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Proceedings
FORMALISE
FORMALISE 2019
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2019 IEEE/ACM 7th International Conference on Formal Methods in Software Engineering (FormaliSE)
May 27 2019 to May 27 2019
Montreal, QC, Canada
ISBN: 978-1-7281-3373-7
Table of Contents
[Title page i]
Freely available from IEEE.
pp. 1-1
[Title page iii]
Freely available from IEEE.
pp. 3-3
Copyright
Freely available from IEEE.
pp. 4-4
Table of contents
Freely available from IEEE.
pp. 5-6
Message from ICSE 2019 General Chair
Freely available from IEEE.
pp. 7-8
Message from the Chairs of FormaliSE 2019
Freely available from IEEE.
pp. 9-9
Program Committee
Freely available from IEEE.
pp. 10-10
Subreviewers
Freely available from IEEE.
pp. 11-11
Epistemic Model Checking of Distributed Commit Protocols with Byzantine Faults
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pp. 1-10
by
Omar Al-Bataineh
,
Mark Reynolds
Rigorous Design and Deployment of IoT Applications
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pp. 11-20
by
Ajay Krishna
,
Michel Le Pallec
,
Radu Mateescu
,
Ludovic Noirie
,
Gwen Salaün
Static Analysis for Worst-Case Battery Utilization
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pp. 21-30
by
Dmitry Ivanov
,
Sibylle Schupp
Clock Reduction in Timed Automata While Preserving Design Parameters
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pp. 31-40
by
Beyazit Yalcinkaya
,
Ebru Aydin Gol
Modular Synthesis of Verified Verifiers of Computation with STV Algorithms
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pp. 85-94
by
Milad K. Ghale
,
Dirk Pattinson
,
Michael Norrish
FASTEN: An Open Extensible Framework to Experiment with Formal Specification Approaches
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pp. 41-50
by
Daniel Ratiu
,
Marco Gario
,
Hannes Schoenhaar
Parallelizable Reachability Analysis Algorithms for Feed-Forward Neural Networks
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pp. 51-60
by
Hoang-Dung Tran
,
Patrick Musau
,
Diego Manzanas Lopez
,
Xiaodong Yang
,
Luan Viet Nguyen
,
Weiming Xiang
,
Taylor T Johnson
Towards Sampling and Simulation-Based Analysis of Featured Weighted Automata
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pp. 61-64
by
Maxime Cordy
,
Axel Legay
,
Sami Lazreg
,
Philippe Collet
Verifying Channel Communication Correctness for a Multi-core Cooperatively Scheduled Runtime Using CSP
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pp. 65-74
by
Jan Bækgaard Pedersen
,
Kevin Chalmers
A Generalized Program Verification Workflow Based on Loop Elimination and SA Form
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pp. 75-84
by
Cláudio Belo Lourenço
,
Maria João Frade
,
Jorge Sousa Pinto
A Vision for Helping Developers Use APIs by Leveraging Temporal Patterns
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pp. 95-98
by
Erick Raelijohn
,
Michalis Famelis
,
Houari Sahraoui
A Proof-Producing Translator for Verilog Development in HOL
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pp. 99-108
by
Andreas Lööw
,
Magnus O. Myreen
On the Formalization of Importance Measures Using HOL Theorem Proving
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pp. 109-118
by
Waqar Ahmad
,
Shahid Ali Murtza
,
Osman Hasan
,
Sofiène Tahar
Author index
Freely available from IEEE.
pp. 119-119
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