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Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)

Nov. 10 2004 to Nov. 12 2004

Sonoma Valley, CA, USA

Table of Contents

Proceedings. Ninth IEEE International High-Level Design Validation and Test Workshop (IEEE Cat. No.04EX940)Freely available from IEEE.pp. i
CommitteesFreely available from IEEE.pp. iv-iv
TTTC: test technology technical councilFreely available from IEEE.pp. ix,x,xi
Session 1: formal techniquesFreely available from IEEE.pp. 1
Session 1: Formal Techniques
Enhancing sequential depth computation with a branch-and-bound algorithmFull-text access may be available. Sign in or learn about subscription options.pp. 3-8
by Chia-Chih Yen, Jing-Yang Jou
Session 2: processor-oriented validationFreely available from IEEE.pp. 23
Session 1: Formal Techniques
Reference model based RTL verification: an integrated approachFull-text access may be available. Sign in or learn about subscription options.pp. 9-13
by W.N.N. Hung, N. Narasimhan
Session 1: Formal Techniques
Table of contentsFull-text access may be available. Sign in or learn about subscription options.pp. v-viii
Session 1: Formal Techniques
Dynamic guiding of bounded property checkingFull-text access may be available. Sign in or learn about subscription options.pp. 15-18
by P.M. Peranandam, R.J. Weiss, J. Ruf, T. Kropf, W. Rosenstiel
Session 1: Formal Techniques
Towards an efficient assertion based verification of SystemC designsFull-text access may be available. Sign in or learn about subscription options.pp. 19-22
by A. Habibi, S. Tahar
Session 2: Processor-oriented Validation
Instruction level test methodology for CPU core software-based self-testingFull-text access may be available. Sign in or learn about subscription options.pp. 25-29
by S. Shamshiri, H. Esmaeilzadeh, Z. Navabi
Session 2: Processor-oriented Validation
Simplifying design and verification for structural hazards and datapaths in pipelined circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 31-36
by J.T. Higgins, M.D. Aagaard
Session 3: decision diagrams for verificationFreely available from IEEE.pp. 47
Session 2: Processor-oriented Validation
ATPG based functional test for data paths: application to a floating point unitFull-text access may be available. Sign in or learn about subscription options.pp. 37-40
by I. Bayraktaroglu, M. d'Abreu
Session 2: Processor-oriented Validation
Formal verification of pipelined processors with load-value predictionFull-text access may be available. Sign in or learn about subscription options.pp. 41-46
by M.N. Velev
Session 3: Decision Diagrams for Verification
On using a 2-domain partitioned OBDD data structure in verificationFull-text access may be available. Sign in or learn about subscription options.pp. 49-54
by T. Feng, L.-C. Wang, K.-T. Cheng, A.C.-C. Lin
Session 3: Decision Diagrams for Verification
Variable ordering for taylor expansion diagramsFull-text access may be available. Sign in or learn about subscription options.pp. 55-59
by D. Gomez-Prado, Q. Ren, S. Askar, M. Ciesielski, E. Boutillon
Session 3: Decision Diagrams for Verification
MODD for CF: a representation for fast evaluation of multiple-output functionsFull-text access may be available. Sign in or learn about subscription options.pp. 61-66
by T.L. Rajaprabhu, A.K. Singh, A.M. Jabir, D.K. Pradhan
Session 4: validation pattern generationFreely available from IEEE.pp. 67
Session 4: Validation Pattern Generation
Functional verification based on the EFSM modelFull-text access may be available. Sign in or learn about subscription options.pp. 69-74
by F. Fummi, C. Marconcini, G. Pravadelli
Session 4: Validation Pattern Generation
Enhancing the efficiency of Bayesian network based coverage directed test generationFull-text access may be available. Sign in or learn about subscription options.pp. 75-80
by M. Braun, S. Fine, A. Ziv
Session 4: Validation Pattern Generation
Mutation-based validation of high-level microprocessor implementationsFull-text access may be available. Sign in or learn about subscription options.pp. 81-86
by J. Campos, H. Al-Asaad
Session 5: Behavioral Modeling
Effects of property ordering in an incremental formal modeling methodologyFull-text access may be available. Sign in or learn about subscription options.pp. 89-94
by Syed Suhaib, Deepak Mathaikutty, Sandeep Shukla
Session 5: Behavioral Modeling
Efficient test-based model generation for legacy reactive systemsFull-text access may be available. Sign in or learn about subscription options.pp. 95-100
by T. Margaria, O. Niese, H. Raffelt, B. Steffen
Session 5: Behavioral Modeling
HLDVT'04 - Ninth Annual IEEE International Workshop on High Level Design Validation and TestFull-text access may be available. Sign in or learn about subscription options.pp. 0_1-0_1
Session 5: behavioral modelingFreely available from IEEE.pp. 87
Session 5: Behavioral Modeling
CopyrightFull-text access may be available. Sign in or learn about subscription options.pp. ii-ii
Session 5: Behavioral Modeling
Model validation for mapping specification behaviors to processing elementsFull-text access may be available. Sign in or learn about subscription options.pp. 101-106
by S. Abdi, D. Gajski
Session 6: fault coverage analysisFreely available from IEEE.pp. 107
Session 6: Fault Coverage Analysis
Test quality for high level structural testFull-text access may be available. Sign in or learn about subscription options.pp. 109-114
by A. AI- Yamani, E.J. McCluskey
Session 6: Fault Coverage Analysis
On code coverage measurement for Verilog-AFull-text access may be available. Sign in or learn about subscription options.pp. 115-120
by Yuan-Bin Sha, Mu-Shun Lee, Mu-Shun Lee
Session 6: Fault Coverage Analysis
On identifying functionally untestable transition faultsFull-text access may be available. Sign in or learn about subscription options.pp. 121-126
by X. Liu, M.S. Hsiao
Session 7: SAT Solving Approaches
CNF formula simplification using implication reasoningFull-text access may be available. Sign in or learn about subscription options.pp. 129-134
by Rajat Arora, M.S. Hsiao
Session 7: SAT Solving Approaches
Dynamic analysis of constraint-variable dependencies to guide SAT diagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 135-140
by V. Durairaj, P. Kalla
Session 7: SAT solving approachesFreely available from IEEE.pp. 127
Session 7: SAT Solving Approaches
Exploiting hypergraph partitioning for efficient Boolean satisfiabilityFull-text access may be available. Sign in or learn about subscription options.pp. 141-146
by V. Duraira, P. Kalla
Session 8: Validation of Network Architectures
An event-based network-on-chip monitoring serviceFull-text access may be available. Sign in or learn about subscription options.pp. 149-154
by C. Ciordas, T. Basten, A. Radulescu, K. Goossens, J. Meerbergen
Session 8: Validation of Network Architectures
Assertion-based power/performance analysis of network processor architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 155-160
by J. Yu, W. Wu, X. Chen, H. Hsieh, J. Yang, F. Balarin
Session 8: Validation of Network Architectures
Validation of the dependability of CAN-based networked systemsFull-text access may be available. Sign in or learn about subscription options.pp. 161-164
by F. Corno, J. Perez, M. Ramasso, M. Reorda, M. Violante
Session 9: High-level Validation
High level hardware validation using hierarchical message sequence chartsFull-text access may be available. Sign in or learn about subscription options.pp. 167-172
by P.K. Murthy, S.R. Rajan, K. Takayama
Session 8: validation of network architecturesFreely available from IEEE.pp. 147
Session 9: High-level Validation
Analysis of the influence of processor hidden registers on the accuracy of fault injection techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 173-178
by D. Gil, J. Gracia, J.C. Baraza, P.J. Gil
Session 9: High-level Validation
On equivalence checking between behavioral and RTL descriptionsFull-text access may be available. Sign in or learn about subscription options.pp. 179-184
by M. Fujita
Session 10: Panel - "Driving the Intelligent Testbench: Are we there yet?"
Panel - "driving the intelligent testbench: are we there yet?"Full-text access may be available. Sign in or learn about subscription options.pp. 187-187
Session 10: Panel - "Driving the Intelligent Testbench: Are we there yet?"
Driving the intelligent testbanch: are we there yet?Full-text access may be available. Sign in or learn about subscription options.pp. 188-188
by H.D. Foster
Session 10: Panel - "Driving the Intelligent Testbench: Are we there yet?"
What happened to the intelligent test bench?Full-text access may be available. Sign in or learn about subscription options.pp. 189-189
by G. Smith
Session 9: high-level validationFreely available from IEEE.pp. 165
Session 10: Panel - "Driving the Intelligent Testbench: Are we there yet?"
Author IndexFull-text access may be available. Sign in or learn about subscription options.pp. 191-191
Session 10: Panel - "Driving the Intelligent Testbench: Are we there yet?"
Back coverFull-text access may be available. Sign in or learn about subscription options.pp. 194-194
Session 10: Panel - "Driving the Intelligent Testbench: Are we there yet?"
Chairs' welcome messageFull-text access may be available. Sign in or learn about subscription options.pp. iii-iii
by A.J. Hu, I.G. Harris
Session 10: panel - "driving the intelligent testbench: are we there yet?"Freely available from IEEE.pp. 185
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