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2017 IEEE International High Level Design Validation and Test Workshop (HLDVT)

Oct. 5 2017 to Oct. 6 2017

Santa Cruz, CA, USA

Table of Contents

Welcome messageFreely available from IEEE.pp. 1-1
Organizing committeeFreely available from IEEE.pp. 1-2
Table of contentsFreely available from IEEE.pp. 1-2
Author indexFreely available from IEEE.pp. 1-2
[Copyright notice]Freely available from IEEE.pp. 1-1
A randomized algorithm for constructing cross-feature tests from single feature testsFull-text access may be available. Sign in or learn about subscription options.pp. 1-8
by Guy Barash, Eitan Farchi
Reachability analysis in RTL circuits using k-induction bounded model checkingFull-text access may be available. Sign in or learn about subscription options.pp. 9-16
by Tonmoy Roy, Michael Hsiao
A novel SAT-based ATPG approach for transition delay faultsFull-text access may be available. Sign in or learn about subscription options.pp. 17-22
by Farzaneh Zokaee, Hossein Sabaghian-Bidgoli, Vahid Janfaza, Payman Behnam, Zainalabedin Navabi
Validation of HMI applications for industrial smart displayFull-text access may be available. Sign in or learn about subscription options.pp. 23-30
by Michele Lora
HES machine: Harmonic equivalent state machine modeling for cyber-physical systemsFull-text access may be available. Sign in or learn about subscription options.pp. 31-38
by Maral Amir, Tony Givargis
Designing cyber-physical systems from natural language descriptionsFull-text access may be available. Sign in or learn about subscription options.pp. 39-44
by Sophia Balkovski, Ian G. Harris
Automated test generation for post silicon microcontroller validationFull-text access may be available. Sign in or learn about subscription options.pp. 45-52
by Pankaj Moharikar, Jayakrishna Guddeti
Repair techniques for aged TSVs in 3D integrated circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 53-58
by Siroos Madani, Kasem Khalil, Bappaditya Dey, Devante Bonton, Magdy Bayoumi
RTL level trace signal selection and coverage estimation during post-silicon validationFull-text access may be available. Sign in or learn about subscription options.pp. 59-66
by Binod Kumar, Kanad Basu, Masahiro Fujita, Virendra Singh
Exploiting sub-graph isomorphism and probabilistic neural networks for the detection of hardware Trojans at RTLFull-text access may be available. Sign in or learn about subscription options.pp. 67-73
by Florenc Demrozi, Riccardo Zucchelli, Graziano Pravadelli
Thread- and data-level parallel simulation in SystemC, a Bitcoin miner case studyFull-text access may be available. Sign in or learn about subscription options.pp. 74-81
by Zhongqi Cheng, Tim Schmidt, Guantao Liu, Rainer Doomer
Design and implementation of FPGA-based muscle conduction velocity tracker in dynamic contractions during the gaitFull-text access may be available. Sign in or learn about subscription options.pp. 82-86
by D. De Venuto, G. Mezzina, V. L. Gallo
3D-DyCAC: Dynamic numerical-based mechanism for reducing crosstalk faults in 3D ICsFull-text access may be available. Sign in or learn about subscription options.pp. 87-90
by Zahra Shirmohammadi, Hadi Zamani Sabzi, Seyed Ghassem Miremadi
An approach to approximate computing: Logic transformations for one-minterm changes in specificationFull-text access may be available. Sign in or learn about subscription options.pp. 91-94
by Masahiro Fujita
On generation of properties from specificationFull-text access may be available. Sign in or learn about subscription options.pp. 95-98
by Keerthikumara Devarajegowda, Wolfgang Ecker
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