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2011 IEEE 17th International Symposium on High Performance Computer Architecture

Feb. 12 2011 to Feb. 16 2011

San Antonio, TX

Table of Contents

Papers
Table of contentsFreely available from IEEE.pp. iii-vii
Keynote address I: Programming the cloudFull-text access may be available. Sign in or learn about subscription options.pp. 1-1
by James Larus
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Achieving uniform performance and maximizing throughput in the presence of heterogeneityFull-text access may be available. Sign in or learn about subscription options.pp. 3-14
by Krishna K. Rangan, Michael D. Powell, Gu-Yeon Wei, David Brooks
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Fg-STP: Fine-Grain Single Thread Partitioning on MulticoresFull-text access may be available. Sign in or learn about subscription options.pp. 15-24
by Rakesn Ranjan, Fernando Latorre, Pedro Marcuello, Antonio Gonzalez
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Thread block compaction for efficient SIMT control flowFull-text access may be available. Sign in or learn about subscription options.pp. 25-36
by Wilson W. L. Fung, Tor M. Aamodt
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Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processorsFull-text access may be available. Sign in or learn about subscription options.pp. 38-49
by Hamid Reza Ghasemi, Stark C. Draper, Nam Sung Kim
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Relaxing non-volatility for fast and energy-efficient STT-RAM cachesFull-text access may be available. Sign in or learn about subscription options.pp. 50-61
by Clinton W. Smullen, Vidyabhushan Mohan, Anurag Nigam, Sudhanva Gurumurthi, Mircea R. Stan
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Shared last-level TLBs for chip multiprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 62-63
by Abhishek Bhattacharjee, Daniel Lustig, Margaret Martonosi
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Bloom Filter Guided Transaction SchedulingFull-text access may be available. Sign in or learn about subscription options.pp. 75-86
by Geoffrey Blake, Ronald G. Dreslinski, Trevor Mudge
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Dynamic parallelization of JavaScript applications using an ultra-lightweight speculation mechanismFull-text access may be available. Sign in or learn about subscription options.pp. 87-98
by Mojtaba Mehrara, Po-Chun Hsu, Mehrzad Samadi, Scott Mahlke
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HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessorFull-text access may be available. Sign in or learn about subscription options.pp. 99-110
by Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tuck
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MOPED: Orchestrating interprocess message data on CMPsFull-text access may be available. Sign in or learn about subscription options.pp. 111-120
by Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Sun
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Addressing system-level trimming issues in on-chip nanophotonic networksFull-text access may be available. Sign in or learn about subscription options.pp. 122-131
by Christopher Nitta, Matthew Farrens, Venkatesh Akella
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Atomic Coherence: Leveraging nanophotonics to build race-free cache coherence protocolsFull-text access may be available. Sign in or learn about subscription options.pp. 132-143
by Dana Vantrease, Mikko H. Lipasti, Nathan Binkert
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CHIPPER: A low-complexity bufferless deflection routerFull-text access may be available. Sign in or learn about subscription options.pp. 144-155
by Chris Fallin, Chris Craik, Onur Mutlu
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Power shifting in Thrifty Interconnection NetworkFull-text access may be available. Sign in or learn about subscription options.pp. 156-167
by Jian Li, Wei Huang, Charles Lefurgy, Lixin Zhang, Wolfgang E. Denzel, Richard R. Treumann, Kun Wang
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Cuckoo directory: A scalable directory for many-core systemsFull-text access may be available. Sign in or learn about subscription options.pp. 169-180
by Michael Ferdman, Pejman Lotfi-Kamran, Ken Balet, Babak Falsafi
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Data-triggered threads: Eliminating redundant computationFull-text access may be available. Sign in or learn about subscription options.pp. 181-192
by Hung-Wei Tseng, Dean M. Tullsen
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Fast thread migration via cache working set predictionFull-text access may be available. Sign in or learn about subscription options.pp. 193-204
by Jeffery A. Brown, Leo Porter, Dean M. Tullsen
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SolarCore: Solar energy driven multi-core architecture power managementFull-text access may be available. Sign in or learn about subscription options.pp. 205-216
by Chao Li, Wangyuan Zhang, Chang-Burm Cho, Tao Li
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Keynote address II: How's the parallel computing revolution going?Full-text access may be available. Sign in or learn about subscription options.pp. 217
by Kathryn S. McKinley
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CloudCache: Expanding and shrinking private cachesFull-text access may be available. Sign in or learn about subscription options.pp. 219-230
by Hyunjin Lee, Sangyeun Cho, Bruce R. Childers
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MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchyFull-text access may be available. Sign in or learn about subscription options.pp. 231-242
by Shekhar Srikantaiah, Emre Kultursay, Tao Zhang, Mahmut Kandemir, Mary Jane Irwin, Yuan Xie
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NUcache: An efficient multicore cache organization based on Next-Use distanceFull-text access may be available. Sign in or learn about subscription options.pp. 243-253
by R Manikantan, Kaushik Rajan, R Govindarajan
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A new server I/O architecture for high speed networksFull-text access may be available. Sign in or learn about subscription options.pp. 255-265
by Guangdeng Liao, Xia Znu, Laxmi Bnuyan
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Essential roles of exploiting internal parallelism of flash memory based solid state drives in high-speed data processingFull-text access may be available. Sign in or learn about subscription options.pp. 266-277
by Feng Chen, Rubao Lee, Xiaodong Zhang
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I-CASH: Intelligently Coupled Array of SSD and HDDFull-text access may be available. Sign in or learn about subscription options.pp. 278-289
by Qing Yang, Jin Ren
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A case for guarded power gating for multi-core processorsFull-text access may be available. Sign in or learn about subscription options.pp. 291-300
by Niti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram
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Beyond block I/O: Rethinking traditional storage primitivesFull-text access may be available. Sign in or learn about subscription options.pp. 301-311
by Xiangyong Ouyang, David Nellans, Robert Wipfel, David Flynn, Dhabaleswar K. Panda
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Efficient data streaming with on-chip accelerators: Opportunities and challengesFull-text access may be available. Sign in or learn about subscription options.pp. 312-320
by Rui Hou, Lixin Zhang, Michael C. Huang, Kun Wang, Hubertus Franke, Yi Ge, Xiaotao Chang
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Hardware/software-based diagnosis of load-store queues using expandable activity logsFull-text access may be available. Sign in or learn about subscription options.pp. 321-331
by Javier Carretero, Xavier Vera, Jaume Abella, Tanausu Ramirez, Matteo Monchiero, Antonio Gonzalez
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Calvin: Deterministic or not? Free will to chooseFull-text access may be available. Sign in or learn about subscription options.pp. 333-334
by Derek R Hower, Polina Dudnik, Mark D. Hill, David A. Wood
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Mercury: A fast and energy-efficient multi-level cell based Phase Change Memory systemFull-text access may be available. Sign in or learn about subscription options.pp. 345-356
by Madhura Joshi, Wangyuan Zhang, Tao Li
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Offline symbolic analysis to infer Total Store OrderFull-text access may be available. Sign in or learn about subscription options.pp. 357-358
by Dongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang Yang
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Safe and efficient supervised memory systemsFull-text access may be available. Sign in or learn about subscription options.pp. 369-380
by Jayaram Bobba, Marc Lupon, Mark D. Hill, David A. Wood
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A quantitative performance analysis model for GPU architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 382-393
by Yao Zhang, John D. Owens
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Abstraction and microarchitecture scaling in early-stage power modelingFull-text access may be available. Sign in or learn about subscription options.pp. 394-405
by Hans Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard Eickemeyer
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HAsim: FPGA-based high-detail multicore simulation using time-division multiplexingFull-text access may be available. Sign in or learn about subscription options.pp. 406-417
by Michael Pellauer, Michael Adler, Michel Kinsy, Angshuman Parashar, Joel Emer
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Checked Load: Architectural support for JavaScript type-checking on mobile processorsFull-text access may be available. Sign in or learn about subscription options.pp. 419-430
by Owen Anderson, Emily Fortuna, Luis Ceze, Susan Eggers
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Exploiting criticality to reduce bottlenecks in distributed uniprocessorsFull-text access may be available. Sign in or learn about subscription options.pp. 431-442
by Behnam Robatmili, Sibi Govindan, Doug Burger, Stephen W. Keckler
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Storage free confidence estimation for the TAGE branch predictorFull-text access may be available. Sign in or learn about subscription options.pp. 443-454
by Andre Seznec
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Architectural framework for supporting operating system survivabilityFull-text access may be available. Sign in or learn about subscription options.pp. 456-465
by Xiaowei Jiang, Yan Solihin
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FREE-p: Protecting non-volatile memory against both hard and soft errorsFull-text access may be available. Sign in or learn about subscription options.pp. 466-477
by Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez
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Practical and secure PCM systems by online detection of malicious write streamsFull-text access may be available. Sign in or learn about subscription options.pp. 478-489
by Moinuddin K. Qureshi, Andre Seznec, Luis A. Lastras, Michele M. Franceschini
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Efficient complex operators for irregular codesFull-text access may be available. Sign in or learn about subscription options.pp. 491-502
by Jack Sampson, Ganesh Venkatesh, Nathan Goulding-Hotta, Saturnino Garcia, Steven Swanson, Michael Bedford Taylor
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Dynamically Specialized Datapaths for energy efficient computingFull-text access may be available. Sign in or learn about subscription options.pp. 503-514
by Venkatraman Govindaraju, Chen-Han Ho, Karthikeyan Sankaralingam
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Hardware/software techniques for DRAM thermal managementFull-text access may be available. Sign in or learn about subscription options.pp. 515-525
by Song Liu, Brian Leung, Alexander Neckar, Seda Ogrenci Memik, Gokhan Memik, Nikos Hardavellas
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ACCESS: Smart scheduling for asymmetric cache CMPsFull-text access may be available. Sign in or learn about subscription options.pp. 527-538
by Xiaowei Jiang, Asit Mishra, Li Zhao, Ravishankar Iyer, Zhen Fang, Sadagopan Srinivasan, Srihari Makineni, Paul Brett, Chita R. Das
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Archipelago: A polymorphic cache design for enabling robust near-threshold operationFull-text access may be available. Sign in or learn about subscription options.pp. 539-550
by Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott Mahlke
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Author indexFreely available from IEEE.pp. 551-553
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