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1992 IEEE/ACM International Conference on Computer-Aided Design

Nov. 8 1992 to Nov. 12 1992

Santa Clara, CA, USA

Table of Contents

Hazard-non-increasing gate-level optimization algorithmsFull-text access may be available. Sign in or learn about subscription options.pp. 631-634
by Kung
Exact two-level minimization of hazard-free logic with multiple-input changesFull-text access may be available. Sign in or learn about subscription options.pp. 626-630
by Nowick, Dill
A comparative study of design for testability methods using high-level and gate-level descriptionsFull-text access may be available. Sign in or learn about subscription options.pp. 620-624
by Chickermane, Lee, Patel
Behavioral synthesis for easy testability in data path schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 616-619
by Lee, Wolf, Jha
Behavioral synthesis for testabilityFull-text access may be available. Sign in or learn about subscription options.pp. 612-615
by Chen, Saab
Area minimization for general floorplansFull-text access may be available. Sign in or learn about subscription options.pp. 606-609
by Pan, Liu
Three-phase chip planning-an improved top-down chip planning strategyFull-text access may be available. Sign in or learn about subscription options.pp. 598-605
by Schurmann, Altmeyer, Zimmermann
Accurate net models for placement improvement by network flow methodsFull-text access may be available. Sign in or learn about subscription options.pp. 594-597
by Doll, Johannes, Sigl
SHILPA: a high-level synthesis system for self-timed circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 587-591
by Akella, Gopalakrishnan
Automatic gate-level synthesis of speed-independent circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 581-586
by Beerel, Meng
Automatic synthesis of 3D asynchronous state machinesFull-text access may be available. Sign in or learn about subscription options.pp. 576-580
by Yun, Dill
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 568-574
by Lakshmi N. Reddy, Irith Pomeranz, Sudhakar M. Reddy
An efficient non-enumerative method to estimate path delay fault coverageFull-text access may be available. Sign in or learn about subscription options.pp. 560-567
by Irith Pomeranz, Sudhakar M. Reddy
Test generation for delay faults in non-scan and partial scan sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 554-559
by Cheng
DAMOCLES: an observer-based approach to design trackingFull-text access may be available. Sign in or learn about subscription options.pp. 546-551
by Vasudevan, Mathys, Tolar
Incorporating design flow management in a framework based CAD systemFull-text access may be available. Sign in or learn about subscription options.pp. 538-545
by Bingley, ten Bosch, van der Wolf
DECOR-tightly integrated design control and observationFull-text access may be available. Sign in or learn about subscription options.pp. 532-537
by Kupitz, Tacken
Precise timing verification of logic circuits under combined delay modelFull-text access may be available. Sign in or learn about subscription options.pp. 526-529
by Kimura, Kashima, Haneda
Valid clocking in wavepipelined circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 518-525
by Lam, Brayton, Sagiovanni-Vincentelli
Exploiting multi-cycle false paths in the performance optimization of sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 510-517
by Ashar, Dey, Malik
Performance optimization of sequential circuits by eliminating retiming bottlenecksFull-text access may be available. Sign in or learn about subscription options.pp. 504-509
by Dey, Potkonjak, Rothweiler
Assignment of global memory elements for multi-process VHDL specificationsFull-text access may be available. Sign in or learn about subscription options.pp. 496-501
by Kramer, Muller
Synthesis of the hardware/software interface in microcontroller-based systemsFull-text access may be available. Sign in or learn about subscription options.pp. 488-495
by Chou, Ortega, Borriello
A partitioning algorithm for system-level synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 482-487
by Menez, Auguin, Boeri, Carriere
Design of system interface modulesFull-text access may be available. Sign in or learn about subscription options.pp. 478-481
by Sun, Brodersen
Perfect-balance planar clock routing with minimal path-lengthFull-text access may be available. Sign in or learn about subscription options.pp. 473-476
by Zhu, Dai
HERO: Hierarchical EMC-constrained routingFull-text access may be available. Sign in or learn about subscription options.pp. 468-472
by Theune, Thiele, Lengauer, Feldmann
Zero skew clock routing in multiple-clock synchronous systemsFull-text access may be available. Sign in or learn about subscription options.pp. 464-467
by Khan, Hossain, Sherwani
A zero-skew clock routing scheme for VLSI circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 458-463
by Li, Jabri
Time domain analysis of nonuniform frequency dependent high-speed interconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 449-453
by Manney, Nakhla, Zhang
An analytical method for finding the maximum crosstalk in lossless-coupled transmission linesFull-text access may be available. Sign in or learn about subscription options.pp. 443-448
by El-Zein, Chowdhury
Efficient techniques for inductance extraction of complex 3-D geometriesFull-text access may be available. Sign in or learn about subscription options.pp. 438-442
by Kamon, Tsuk, Smithhisler, White
Optimal replication for min-cut partitioningFull-text access may be available. Sign in or learn about subscription options.pp. 432-435
by Hwang, El Gamal
A probabilistic multicommodity-flow solution to circuit clustering problemsFull-text access may be available. Sign in or learn about subscription options.pp. 428-431
by Yeh, Cheng, Lin
A new approach to effective circuit clusteringFull-text access may be available. Sign in or learn about subscription options.pp. 422-427
by Hagen, Kahng
A new algorithm for the binate covering problem and its application to the minimization of Boolean relationsFull-text access may be available. Sign in or learn about subscription options.pp. 417-420
by Jeong, Somenzi
ProperSYN: A portable parallel algorithm for logic synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 412-416
by De, Ramkumar, Banerjee
Efficient Boolean function matchingFull-text access may be available. Sign in or learn about subscription options.pp. 408-411
by Burch, Long
On average power dissipation and random pattern testability of CMOS combinational logic networksFull-text access may be available. Sign in or learn about subscription options.pp. 402-407
by Shen, Ghosh, Devadas, Keutzer
System-level routing of mixed-signal ASICs in WRENFull-text access may be available. Sign in or learn about subscription options.pp. 394-399
by Mitra, Nag, Rutenbar, Carley
A wire-length minimization algorithm for single-layer layoutsFull-text access may be available. Sign in or learn about subscription options.pp. 390-393
by Chen, Sarrafzadeh
Detailed layer assignment for MCM routingFull-text access may be available. Sign in or learn about subscription options.pp. 386-389
by Sriram, Kang
Maze router without a grid mapFull-text access may be available. Sign in or learn about subscription options.pp. 382-385
by Soukup
A logic simulation engine based on a modified data flow architectureFull-text access may be available. Sign in or learn about subscription options.pp. 377-380
by Mahmood, Baker, Herath, Jayasumana
Reconfigurable machine and its application to logic diagnosisFull-text access may be available. Sign in or learn about subscription options.pp. 373-376
by Suganuma, Murata, Nakata, Nagata, Tomita, Hirano
Parallel logic and fault simulation algorithms for shared memory vector machinesFull-text access may be available. Sign in or learn about subscription options.pp. 369-372
by Bataineh, Ozguner, Szauter
Ravel: assinged-delay compiled-code logic simulationFull-text access may be available. Sign in or learn about subscription options.pp. 364-368
by Shriver, Sakallah
Accurate layout area and delay modeling for system level designFull-text access may be available. Sign in or learn about subscription options.pp. 355-361
by Ramachandran, Kurdahi, Gajski, Wu, Chaiyakul
Timing analysis in high-level synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 349-354
by Kuehlmann, Bergamaschi
False loops through resource sharing (logic CAD)Full-text access may be available. Sign in or learn about subscription options.pp. 345-348
by Stok
FICOM: a framework for incremental consistency maintenance in multi-representation, structural VLSI databasesFull-text access may be available. Sign in or learn about subscription options.pp. 336-343
by Armstrong, Allen
Equivalent design representations and transformations for interactive schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 332-335
by Ang, Dutt
An efficient multi-view design model for real-time interactive synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 328-331
by Wu, Hadley, Gajski
Behavioral simulation for noise in mixed-mode samples-data systemsFull-text access may be available. Sign in or learn about subscription options.pp. 322-326
by Liu, Sangiovanni-Vincentelli
Accurate simplification of large symbolic formulaeFull-text access may be available. Sign in or learn about subscription options.pp. 318-321
by Fernandez, Rodriguez-Vazquez, Martin, Huertas
Lazy-expansion symbolic expression approximation in SYNAPFull-text access may be available. Sign in or learn about subscription options.pp. 310-317
by Seda, Degrauwe, Fichtner
Maximally fast and arbitrarily fast implementation of linear computations (circuit layout CAD)Full-text access may be available. Sign in or learn about subscription options.pp. 304-308
by Potkonjak, Rabaey
HYPER-LP: a system for power minimization using architectural transformationsFull-text access may be available. Sign in or learn about subscription options.pp. 300-303
by Chandrakasan, Potkonjak, Rabaey, Brodersen
Area optimization of multi-functional processing unitsFull-text access may be available. Sign in or learn about subscription options.pp. 292-299
by van der Werf, Peek, Aarts, Van Meerbergen, Lippens, Verhaegh
Efficiency improvements for force-directed schedulingFull-text access may be available. Sign in or learn about subscription options.pp. 286-291
by Verhaegh, Lippens, Aarts, Korst, van der Werf, van Meerbergen
Efficient partitioning and analysis of digital CMOS-circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 280-283
by Hubner, Vierhaus
On the generation of small dictionaries for fault locationFull-text access may be available. Sign in or learn about subscription options.pp. 272-279
by Irith Pomeranz, Sudhakar M. Reddy
E-PROOFS: A CMOS bridging fault simulatorFull-text access may be available. Sign in or learn about subscription options.pp. 268-271
by Greenstein, Patel
An optimal probe testing algorithm for the connectivity verification of MCM substratesFull-text access may be available. Sign in or learn about subscription options.pp. 264-267
by Yao, Chou, Cheng, Hu
ETA: electrical-level timing analysisFull-text access may be available. Sign in or learn about subscription options.pp. 258-262
by Brashear, Holberg, Mercer, Pillage
A methodology for improved circuit simulation efficiency via topology-based variable accuracy device modelingFull-text access may be available. Sign in or learn about subscription options.pp. 254-257
by Michaels, Strojwas
Analytic macromodeling and simulation of tightly-coupled mixed analog-digital circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 244-247
by Chang, Yang
Optimal synthesis of multichip architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 238-241
by Gebotys
A scheduling method by stepwise expansion in high-level synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 234-237
by Komi, Yamada, Fukunaga
An effective methodology for functional pipeliningFull-text access may be available. Sign in or learn about subscription options.pp. 230-233
by Lee, Wu, Gajski, Lin
Automatic test generation for linear digital systems with bi-level search using matrix transform methodsFull-text access may be available. Sign in or learn about subscription options.pp. 224-228
by Roy, Chatterjee, Patel, Abraham, d'Abreu
Portable parallel test generation for sequential circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 220-223
by Ramkumar, Banerjee
CRIS: A test cultivation program for sequential VLSI circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 216-219
by Saab, Saab, Abraham
A probabilistic timing approach to hot-carrier effect estimationFull-text access may be available. Sign in or learn about subscription options.pp. 210-213
by Li, Stamoulis, Hajj
Power estimation tool for sub-micron CMOS VLSI circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 204-209
by Rouatbi, Haroun, Al-Khalili
Delay and bus current evaluation in CMOS logic circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 198-203
by Nabavi-Lishi, Rumin
Verification of asynchronous interface circuits with bounded wire delaysFull-text access may be available. Sign in or learn about subscription options.pp. 188-195
by Devadas, Keutzer, Malik, Wang
Automatic generation and verification of sufficient correctness properties for synchronous processorsFull-text access may be available. Sign in or learn about subscription options.pp. 183-187
by Van Aelten, Liao, Allen, Devadas
Verification of systems containing countersFull-text access may be available. Sign in or learn about subscription options.pp. 179-182
by Macii, Plessier, Somenzi
Automatic compositional minimization in CTL model checkingFull-text access may be available. Sign in or learn about subscription options.pp. 172-178
by Chiodo, Shiple, Sangiovanni-Vincentelli, Brayton
Automatic differentiation in circuit simulation and device modelingFull-text access may be available. Sign in or learn about subscription options.pp. 248-253
by Feldmann, Melville, Moinian
MOSAIC: a tile-based datapath layout generatorFull-text access may be available. Sign in or learn about subscription options.pp. 166-170
by Suzuki, Yamamoto, Yuyama, Hirasawa
An optimal chip compaction method based on shortest path algorithm with automatic jog insertionFull-text access may be available. Sign in or learn about subscription options.pp. 162-165
by Awashima, Yamamoto, Sato, Ohtsuki
Cloning techniques for hierarchical compactionFull-text access may be available. Sign in or learn about subscription options.pp. 158-161
by Varadarajan, Bamji
HIMALAYAS-A hierarchical compaction system with a minimized constraint setFull-text access may be available. Sign in or learn about subscription options.pp. 150-157
by Lee, Tang
Using constraint geometry to determine maximum rate pipeline clockingFull-text access may be available. Sign in or learn about subscription options.pp. 142-148
by Chang, Davidson, Sakallah
Identification of critical paths in circuits with level-sensitive latchesFull-text access may be available. Sign in or learn about subscription options.pp. 137-141
by Burks, Sakallah, Mudge
Verifying clock schedulesFull-text access may be available. Sign in or learn about subscription options.pp. 124-131
by Szymanski, Shenoy
On the verification of state-coding in STGsFull-text access may be available. Sign in or learn about subscription options.pp. 118-122
by Lin, Lin
A generalized state assignment theory for transformations on signal transition graphsFull-text access may be available. Sign in or learn about subscription options.pp. 112-117
by Vanbekbergen, Lin, Goossens, De Man
A unified signal transition graph model for asynchronous control circuit synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 104-111
by Yakovlev, Lavagno, Sangiovanni-Vincentelli
Exhaustive simulation need not require an exponential number of testsFull-text access may be available. Sign in or learn about subscription options.pp. 98-101
by Brand
McPOWER: a Monte Carlo approach to power estimationFull-text access may be available. Sign in or learn about subscription options.pp. 90-97
by Burch, Najm, Yang, Trick
Timing distribution in VHDL behavioral modelsFull-text access may be available. Sign in or learn about subscription options.pp. 82-89
by Gadagkar, Armstrong
Numerical integration algorithms and asymptotic waveform evaluation (AWE)Full-text access may be available. Sign in or learn about subscription options.pp. 76-79
by Alaybeyi, Lee, Rohrer
Extension of the asymptotic waveform evaluation technique with the method of characteristicsFull-text access may be available. Sign in or learn about subscription options.pp. 71-75
by Bracken, Raghavan, Rohrer
AWE macromodels of VLSI interconnect for circuit simulationFull-text access may be available. Sign in or learn about subscription options.pp. 64-70
by Kim, Gopal, Pillage
Rectification method for lookup-table type FPGA'sFull-text access may be available. Sign in or learn about subscription options.pp. 54-61
by Kukimoto, Fujita
An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designsFull-text access may be available. Sign in or learn about subscription options.pp. 48-53
by Cong, Ding
A tutorial on logic synthesis for lookup-table based FPGAsFull-text access may be available. Sign in or learn about subscription options.pp. 40-47
by Francis
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