Computer-Aided Design, International Conference on
Nov. 7 1999 to Nov. 11 1999
San Jose, CA
ISSN: 1092-3152
ISBN: 0-7803-5832-5
Table of Contents
Session 1A: Sequential and Datapath Optimization
Session 1A: Sequential and Datapath Optimization
Session 1A: Sequential and Datapath Optimization
Session 1B: Placement I
Session 1C: BDDs in Formal Verification
Session 1C: BDDs in Formal Verification
Session 1C: BDDs in Formal Verification
Session 1D: Analog and Mixed-Signal
Session 1D: Analog and Mixed-Signal
Session 2A: Power Optimization
Session 2A: Power Optimization
Session 2A: Power Optimization
Session 2B: Placement II
Session 2B: Placement II
Session 2C: Domino- and ATPG-Based Logic Synthesis
Session 2C: Domino- and ATPG-Based Logic Synthesis
Session 2C: Domino- and ATPG-Based Logic Synthesis
Session 2D: Electrical and Thermal Analysis
Session 2D: Electrical and Thermal Analysis
Session 2D: Electrical and Thermal Analysis
Session 3A: Automatic Test Pattern Generation
Session 3A: Automatic Test Pattern Generation
Session 3A: Automatic Test Pattern Generation
Session 3B: Routing
Session 3C: Logic-Level Performance Optimization
Session 3C: Logic-Level Performance Optimization
Session 3C: Logic-Level Performance Optimization
Session 3C: Logic-Level Performance Optimization
Session 3D: Practical Issues in Order Reduction
Session 3D: Practical Issues in Order Reduction
Session 3D: Practical Issues in Order Reduction
Session 3D: Practical Issues in Order Reduction
Session 4B: Embedded Tutorial
Session 5A: Timing Optimization
Session 5A: Timing Optimization
Session 5B: Compilation Techniques for Embedded Systems
Session 5B: Compilation Techniques for Embedded Systems
Session 5B: Compilation Techniques for Embedded Systems
Session 5C: High Level Power Exploration
Session 5C: High Level Power Exploration
Session 5C: High Level Power Exploration
Session 5C: High Level Power Exploration
Session 5D: Analog and Mixed Signal Test
Session 5D: Analog and Mixed Signal Test
Session 5D: Analog and Mixed Signal Test
Session 6A: Globally Untimed Locally Timed Design
Session 6A: Globally Untimed Locally Timed Design
Session 6A: Globally Untimed Locally Timed Design
Session 6B: Task-Level Analysis and Synthesis
Session 6B: Task-Level Analysis and Synthesis
Session 6C: Floorplanning and Partitioning
Session 6C: Floorplanning and Partitioning
Session 6C: Floorplanning and Partitioning
Session 6D: Advances in Model Order Reduction
Session 6D: Advances in Model Order Reduction
Session 6D: Advances in Model Order Reduction
Session 7B: Graph Techniques for Design Optimization
Session 7B: Graph Techniques for Design Optimization
Session 7B: Graph Techniques for Design Optimization
Session 7B: Graph Techniques for Design Optimization
Session 7D: Techniques for Parasitic Extraction
Session 7D: Techniques for Parasitic Extraction
Session 7D: Techniques for Parasitic Extraction
Session 8B: Embedded Tutorial
Session 9A: Test Pattern Analysis
Session 9A: Test Pattern Analysis