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2002 IEEE/ACM International Conference on Computer Aided Design (ICCAD)

Nov. 10 2002 to Nov. 14 2002

San Jose, CA, USA

Table of Contents

IEEE/ACM International Conference on Computer Aided Design. IEEE/ACM Digest of Technical Papers (Cat. No.02CH37391)Freely available from IEEE.
Comprehensive frequency-dependent substrate noise analysis using boundary element methodsFull-text access may be available. Sign in or learn about subscription options.pp. 2,3,4,5,6,7,8,9
by Hongmei Li, J. Carballido, H.H. Yu, V.I. Okhmatovski, E. Rosenbaum, A.C. Cangellaris
Theoretical and practical validation of combined BEM/FEM substrate resistance modelingFull-text access may be available. Sign in or learn about subscription options.pp. 10,11,12,13,14,15
by E. Schrik, P.M. Dewilde, N.P. van der Meijs
Implicit treatment of substrate and power-ground losses in return-limited inductance extractionFull-text access may be available. Sign in or learn about subscription options.pp. 16,17,18,19,20,21,22
by D. Sitaram, Yu Zheng, K.L. Shepard
Minimizing power across multiple technology and design levelsFull-text access may be available. Sign in or learn about subscription options.pp. 24,25,26,27
by T. Sakurai
Optimization and control of V/sub DD/ and V/sub TH/ for low-power, high-speed CMOS designFull-text access may be available. Sign in or learn about subscription options.pp. 28,29,30,31,32,33,34
by T. Kuroda
Methods for true power minimizationFull-text access may be available. Sign in or learn about subscription options.pp. 35,36,37,38,39,40,41,42
by R.W. Brodersen, M.A. Horowitz, D. Markovic, B. Nikolic, V. Stojanovic
A novel framework for multilevel routing considering routability and performanceFull-text access may be available. Sign in or learn about subscription options.pp. 44,45,46,47,48,49,50
by Shih-Ping Lin, Yao-Wen Chang
An enhanced multilevel routing systemFull-text access may be available. Sign in or learn about subscription options.pp. 51,52,53,54,55,56,57,58
by J. Cong, M. Xie, Y. Zhang
Track assignment: a desirable intermediate step between global routing and detailed routingFull-text access may be available. Sign in or learn about subscription options.pp. 59,60,61,62,63,64,65,66
by S. Batterywala, N. Shenoy, W. Nicholls, H. Zhou
ECO algorithms for removing overlaps between power rails and signal wires [IC layout]Full-text access may be available. Sign in or learn about subscription options.pp. 67,68,69,70,71,72,73,74
by Hua Xiang, Kai-Yuan Chao, D.F. Wong
Fast seed computation for reseeding shift register in test pattern compressionFull-text access may be available. Sign in or learn about subscription options.pp. 76,77,78,79,80,81
by N. Oh, R. Kapur, T.W. Williams
On undetectable faults in partial scan circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 82,83,84,85,86
by I. Pomeranz, S.M. Reddy
Conflict driven techniques for improving deterministic test pattern generationFull-text access may be available. Sign in or learn about subscription options.pp. 87,88,89,90,91,92,93
by Chen Wang, S.M. Reddy, I. Pomeranz, Xijiang Lin, J. Rajski
On theoretical and practical considerations of path selection for delay fault testingFull-text access may be available. Sign in or learn about subscription options.pp. 94,95,96,97,98,99,100
by Jing-Jia Liou, L.-C. Wang, Kwang-Ting Cheng
Interface specification for reconfigurable componentsFull-text access may be available. Sign in or learn about subscription options.pp. 102,103,104,105,106,107,108,109
by Satnam Singh
Interconnect-aware high-level synthesis for low powerFull-text access may be available. Sign in or learn about subscription options.pp. 110,111,112,113,114,115,116,117
by Lin Zhong, N.K. Jha
Predictability: definition, analysis and optimization [VLSI design]Full-text access may be available. Sign in or learn about subscription options.pp. 118,119,120,121
by A. Srivastava, M. Sarrafzadeh
Simplifying Boolean constraint solving for random simulation-vector generationFull-text access may be available. Sign in or learn about subscription options.pp. 123,124,125,126,127
by Jun Yuan, K. Albin, A. Aziz, C. Pixley
Specifying and verifying imprecise sequential datapaths by arithmetic transformsFull-text access may be available. Sign in or learn about subscription options.pp. 128,129,130,131
by K. Radecka, Z. Zilic
Convertibility verification and converter synthesis: two faces of the same coin [IP block interfaces]Full-text access may be available. Sign in or learn about subscription options.pp. 132,133,134,135,136,137,138,139
by R. Passerone, L. de Alfaro, T.A. Henzinger, A.L. Sangiovanni-Vincentelli
Subthreshold leakage modeling and reduction techniques [IC CAD tools]Full-text access may be available. Sign in or learn about subscription options.pp. 141,142,143,144,145,146,147,148
by J. Kao, S. Narendra, A. Chandrakasan
Symbolic pointer analysisFull-text access may be available. Sign in or learn about subscription options.pp. 150,151,152,153,154,155,156,157
by Jianwen Zhu
Dynamic compilation for energy adaptationFull-text access may be available. Sign in or learn about subscription options.pp. 158,159,160,161,162,163
by P. Unnikrishnan, G. Chen, M. Kandemir, D.R. Mudgett
Hardware/software partitioning of software binariesFull-text access may be available. Sign in or learn about subscription options.pp. 164,165,166,167,168,169,170
by G. Stitt, F. Vahid
A novel net weighting algorithm for timing-driven placementFull-text access may be available. Sign in or learn about subscription options.pp. 172,173,174,175,176
by T. Kong
Timing-driven placement using design hierarchy guided constraint generationFull-text access may be available. Sign in or learn about subscription options.pp. 177,178,179,180
by Xiaojian Yang, Bo-Kyung Choi, M. Sarrafzadeh
Multi-objective circuit partitioning for cutsize and path-based delay minimizationFull-text access may be available. Sign in or learn about subscription options.pp. 181,182,183,184,185
by C. Ababei, S. Navaratnasothie, K. Bazargan, G. Karypis
A hybrid ASIC and FPGA architectureFull-text access may be available. Sign in or learn about subscription options.pp. 187,188,189,190,191,192,193,194
by P.S. Zuchowski, C.B. Reynolds, R.J. Grupp, S.G. Davis, B. Cremen, B. Troxel
Managing power and performance for system-on-chip designs using Voltage IslandsFull-text access may be available. Sign in or learn about subscription options.pp. 195,196,197,198,199,200,201,202
by D.E. Lackey, P.S. Zuchowski, T.R. Bednar, D.W. Stout, S.W. Gould, J.M. Cohn
Sub-90 nm technologies-challenges and opportunities for CADFull-text access may be available. Sign in or learn about subscription options.pp. 203,204,205,206
by T. Karnik, S. Borkar, V. De
A local circuit topology for inductive parasiticsFull-text access may be available. Sign in or learn about subscription options.pp. 208,209,210,211,212,213,214
by A. Pacelli
INDUCTWISE: inductance-wise interconnect simulator and extractorFull-text access may be available. Sign in or learn about subscription options.pp. 215,216,217,218,219,220
by Tsung-Hao Chen, C. Luk, Hyungsuk Kim, C. Chung-Ping Chen
A precorrected-FFT method for simulating on-chip inductanceFull-text access may be available. Sign in or learn about subscription options.pp. 221,222,223,224,225,226,227
by Haitian Hu, D.T. Blaauw, V. Zolotov, K. Gala, Min Zhao, R. Panda, S.S. Sapatnekar
On the difference between two widely publicized methods for analyzing oscillator phase behaviorFull-text access may be available. Sign in or learn about subscription options.pp. 229,230,231,232,233
by P. Vanassche, G. Gielen, W. Sansen
A behavioral simulation tool for continuous-time /spl Delta//spl Sigma/ modulatorsFull-text access may be available. Sign in or learn about subscription options.pp. 234,235,236,237,238,239
by K. Francken, M. Vogels, E. Martens, G. Gielen
Making Fourier-envelope simulation robustFull-text access may be available. Sign in or learn about subscription options.pp. 240,241,242,243,244,245
by J. Roychowdhury
Optimal buffered routing path constructions for single and multiple clock domain systemsFull-text access may be available. Sign in or learn about subscription options.pp. 247,248,249,250,251,252,253
by S. Hassoun, C.J. Alpert, M. Thiagarajan
Shaping interconnect for uniform current densityFull-text access may be available. Sign in or learn about subscription options.pp. 254,255,256,257,258,259
by Muzhou Shao, D.F. Wong, Youxin Gao, Li-Pen Yuan, Huijing Cao
Non-tree routing for reliability and yield improvementFull-text access may be available. Sign in or learn about subscription options.pp. 260,261,262,263,264,265,266
by A.B. Kahng, Bao Liu, I.I. Mandoiu
Concurrent flip-flop and repeater insertion for high performance integrated circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 268,269,270,271,272,273
by P. Cocchini
Throughput-driven IC communication fabric synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 274,275,276,277,278,279
by Tao Lin, L.T. Pileggi
Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnectsFull-text access may be available. Sign in or learn about subscription options.pp. 280,281,282,283,284
by H. Shah, P. Shiu, B. Bell, M. Aldredge, N. Sopory, J. Davis
Test-model based hierarchical DFT synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 286,287,288,289,290,291,292,293
by S. Ramnath, F. Neuveux, M. Hirech, F. Ng
Characteristic faults and spectral information for logic BISTFull-text access may be available. Sign in or learn about subscription options.pp. 294,295,296,297,298
by Xiaoding Chen, M.S. Hsiao
A novel scan architecture for power-efficient, rapid test [sequential circuits]Full-text access may be available. Sign in or learn about subscription options.pp. 299,300,301,302,303
by O. Sinanoglu, A. Orailoglu
Optimization of a fully integrated low power CMOS GPS receiverFull-text access may be available. Sign in or learn about subscription options.pp. 305,306,307,308
by P. Vancorenland, P. Coppejans, W. De Cock, P. Leroux, M. Steyaert
Analysis and optimization of substrate noise coupling in single-chip RF transceiver designFull-text access may be available. Sign in or learn about subscription options.pp. 309,310,311,312,313,314,315,316
by A. Koukab, K. Banerjee, M. Declercq
Design of pipeline analog-to-digital converters via geometric programmingFull-text access may be available. Sign in or learn about subscription options.pp. 317,318,319,320,321,322,323,324
by M. del Mar Hershenson
Proximity templates for modeling of skin and proximity effects on packages and high frequency interconnectFull-text access may be available. Sign in or learn about subscription options.pp. 326,327,328,329,330,331,332,333
by L. Daniel, A. Sangiovanni-Vincentelli, J. White
Transmission line design of clock treesFull-text access may be available. Sign in or learn about subscription options.pp. 334,335,336,337,338,339,340
by R. Escovar, R. Suaya
On-chip interconnect modeling by wire duplicationFull-text access may be available. Sign in or learn about subscription options.pp. 341,342,343,344,345,346
by G. Zhong, C.-K. Koh, K. Roy
A case for CMOS/nano co-designFull-text access may be available. Sign in or learn about subscription options.pp. 348,349,350,351,352
by M.M. Ziegler, M.R. Stan
Reversible logic circuit synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 353,354,355,356,357,358,359,360
by V.V. Shende, A.K. Prasad, I.L. Markov, J.P. Hayes
Extraction and LVS for mixed-domain integrated MEMS layoutsFull-text access may be available. Sign in or learn about subscription options.pp. 361,362,363,364,365,366
by B. Baidya, T. Mukherjee
Schematic-based lumped parameterized behavioral modeling for suspended MEMSFull-text access may be available. Sign in or learn about subscription options.pp. 367,368,369,370,371,372,373
by Q. Jing, T. Mukherjee, G.K. Fedder
Standby power optimization via transistor sizing and dual threshold voltage assignmentFull-text access may be available. Sign in or learn about subscription options.pp. 375,376,377,378
by M. Ketkar, S.S. Sapatnekar
Power efficiency of voltage scaling in multiple clock multiple voltage coresFull-text access may be available. Sign in or learn about subscription options.pp. 379,380,381,382,383,384,385,386
by A. Iyer, D. Marculescu
Optimized power-delay curve generation for standard cell ICsFull-text access may be available. Sign in or learn about subscription options.pp. 387,388,389,390,391,392,393,394
by M. Vujkovic, C. Sechen
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing stepFull-text access may be available. Sign in or learn about subscription options.pp. 395,396,397,398,399,400,401,402
by H. Tennakoon, C. Sechen
A Markov chain sequence generator for power macromodelingFull-text access may be available. Sign in or learn about subscription options.pp. 404,405,406,407,408,409,410,411
by Xun Liu, M.C. Papaefthymiou
Circuit power estimation using pattern recognition techniquesFull-text access may be available. Sign in or learn about subscription options.pp. 412,413,414,415,416,417
by Lipeng Cao
Estimation of signal arrival times in the presence of delay noiseFull-text access may be available. Sign in or learn about subscription options.pp. 418,419,420,421,422
by S. Bhardwaj, S.B.K. Vrudhula, D. Blaauw
CAD computation for manufacturability: can we save VLSI technology from itself?Full-text access may be available. Sign in or learn about subscription options.pp. 424,425,426,427,428,429,430,431
by M. Lavin, L. Liebmann
Molecular electronics: devices, systems and tools for gigagate, gigabit chipsFull-text access may be available. Sign in or learn about subscription options.pp. 433-440
by M. Butts, A. DeHon, S.C. Goldstein
Conflict driven learning in a quantified Boolean satisfiability solverFull-text access may be available. Sign in or learn about subscription options.pp. 442,443,444,445,446,447,448,449
by Lintao Zhang, S. Malik
Generic ILP versus specialized 0-1 ILP: an updateFull-text access may be available. Sign in or learn about subscription options.pp. 450,451,452,453,454,455,456,457
by F.A. Aloul, A. Ramani, I.L. Markov, K.A. Sakallah
Binary time-frame expansion [circuit verification]Full-text access may be available. Sign in or learn about subscription options.pp. 458,459,460,461,462,463,464
by F. Fallah
Fast methods for simulation of biomolecule electrostaticsFull-text access may be available. Sign in or learn about subscription options.pp. 466,467,468,469,470,471,472,473
by S.S. Kuo, M.D. Altman, Bardhan JP, B. Tidor, J.K. White
Efficient mixed-domain analysis of electrostatic MEMSFull-text access may be available. Sign in or learn about subscription options.pp. 474,475,476,477
by Gang Li, N.R. Aluru
Expression of Concern: FastMag: a 3-D magnetostatic inductance extraction program for structures with permeable materialsFull-text access may be available. Sign in or learn about subscription options.pp. 478-484
by Y. Massoud, J. White
Analog circuit sizing based on formal methods using affine arithmeticFull-text access may be available. Sign in or learn about subscription options.pp. 486,487,488,489
by A. Lemke, L. Hedrich, E. Barke
SiSMA: a statistical simulator for mismatch analysis of MOS ICsFull-text access may be available. Sign in or learn about subscription options.pp. 490,491,492,493,494,495,496
by G. Biagetti, S. Orcioni, L. Signoracci, C. Turchetti, P. Crippa, M. Alessandrini
Efficient solution space exploration based on segment trees in analog placement with symmetry constraintsFull-text access may be available. Sign in or learn about subscription options.pp. 497,498,499,500,501,502
by F. Balasa, S.C. Maruvada, K. Krishnamoorthy
Post global routing RLC crosstalk budgetingFull-text access may be available. Sign in or learn about subscription options.pp. 504,505,506,507,508,509
by Jinjun Xiong, Jun Chen, J. Ma, Lei He
A technology-independent CAD tool for ESD protection device extraction-ESDExtractorFull-text access may be available. Sign in or learn about subscription options.pp. 510,511,512,513
by R.Y. Zhan, H.G. Feng, Q. Wu, G. Chen, X.K. Guan, A.Z. Wang
On mask layout partitioning for electron projection lithographyFull-text access may be available. Sign in or learn about subscription options.pp. 514,515,516,517,518
by Ruiqi Tian, Ronggang Yu, Xiaoping Tang, D.F. Wong
High capacity and automatic functional extraction tool for industrial VLSI circuit designsFull-text access may be available. Sign in or learn about subscription options.pp. 520,521,522,523,524,525
by S. Novakovsky, S. Shyman, Z. Hanna
Combinational equivalence checking through function transformationFull-text access may be available. Sign in or learn about subscription options.pp. 526,527,528,529,530,531,532,533
by Hee Hwan Kwak, In-Ho Moon, J.H. Kukula, T.R. Shiple
GSTE through a case study [digital IC verification]Full-text access may be available. Sign in or learn about subscription options.pp. 534,535,536,537,538,539,540,541
by J. Yang, A. Goel
Whirlpool PLAs: a regular logic structure and their synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 543,544,545,546,547,548,549,550
by Fan Mo, R.K. Brayton
Metrics for structural logic synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 551,552,553,554,555,556
by P. Kudva, A. Sullivan, W. Dougherty
Simplification of non-deterministic multi-valued networksFull-text access may be available. Sign in or learn about subscription options.pp. 557,558,559,560,561,562
by A. Mishchenko, R. Brayton
High-level synthesis of distributed logic-memory architecturesFull-text access may be available. Sign in or learn about subscription options.pp. 564,565,566,567,568,569,570,571
by Chao Huang, S. Ravi, A. Raghunathan, N.K. Jha
An energy-conscious algorithm for memory port allocationFull-text access may be available. Sign in or learn about subscription options.pp. 572,573,574,575,576
by P.R. Panda, L. Chitturi
Energy efficient address assignment through minimized memory row switchingFull-text access may be available. Sign in or learn about subscription options.pp. 577,578,579,580,581
by S. Hettiaratchi, P.Y.K. Cheung, T.J.W. Clarke
Refining switching window by time slots for crosstalk noise calculationFull-text access may be available. Sign in or learn about subscription options.pp. 583,584,585,586
by Pinhong Chen, Y. Kukimoto, K. Keutzer
Noise propagation and failure criteria for VLSI designsFull-text access may be available. Sign in or learn about subscription options.pp. 587,588,589,590,591,592,593,594
by V. Zolotov, D. Blaauw, S. Sirichotiyakul, M. Becer, C. Oh, R. Panda, A. Grinshpon, R. Levy
Efficient crosstalk noise modeling using aggressor and tree reductionsFull-text access may be available. Sign in or learn about subscription options.pp. 595,596,597,598,599,600
by Li Ding, D. Blaauw, P. Mazumder
Bit-level scheduling of heterogeneous behavioural specificationsFull-text access may be available. Sign in or learn about subscription options.pp. 602,603,604,605,606,607,608
by M.C. Molina, J.M. Mendias, R. Hermida
Coupling-aware high-level interconnect synthesis for low powerFull-text access may be available. Sign in or learn about subscription options.pp. 609,610,611,612,613
by Chun-Gi Lyuh, Taewhan Kim, Ki-Wook Kim
Layout-driven resource sharing in high-level synthesisFull-text access may be available. Sign in or learn about subscription options.pp. 614,615,616,617,618
by Junhyung Um, Jae-hoon Kim, Taewhan Kim
A delay metric for RC circuits based on the Weibull distributionFull-text access may be available. Sign in or learn about subscription options.pp. 620-624
by F. Liu, C. Kashyap, C.J. Alpert
WTA - Waveform-based Timing Analysis for deep submicron circuitsFull-text access may be available. Sign in or learn about subscription options.pp. 625,626,627,628,629,630,631
by L. McMurchie, C. Sechen
General framework for removal of clock network pessimismFull-text access may be available. Sign in or learn about subscription options.pp. 632,633,634,635,636,637,638,639
by J. Zejda, P. Frain
Synthesis of custom processors based on extensible platformsFull-text access may be available. Sign in or learn about subscription options.pp. 641,642,643,644,645,646,647,648
by Fei Sun, S. Ravi, A. Raghunathan, N.K. Jha
Efficient instruction encoding for automatic instruction set design of configurable ASIPsFull-text access may be available. Sign in or learn about subscription options.pp. 649,650,651,652,653,654
by Jong-eun Lee, Kiyoung Choi, N. Dutt
Synthesis of customized loop caches for core-based embedded systemsFull-text access may be available. Sign in or learn about subscription options.pp. 655,656,657,658,659,660,661,662
by S. Cotterell, F. Vahid
A hierarchical modeling framework for on-chip communication architectures [SOC]Full-text access may be available. Sign in or learn about subscription options.pp. 663,664,665,666,667,668,669,670
by Xinping Zhu, S. Malik
A new enhanced SPFD rewiring algorithm [logic IC layout]Full-text access may be available. Sign in or learn about subscription options.pp. 672,673,674,675,676,677,678
by J. Cong, J.Y. Lin, W. Long
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